AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 52

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
SPI Instruction Word (16 Bits)
The MSB of the 16-bit instruction word is R/
whether the instruction is a read or a write. The next two bits, W1
and W0, indicate the number of bytes in the transfer (see
The final 13 bits are the register address (A12 to A0), which indi-
cates the starting register address of the read/write operation
(see
SPI MSB/LSB First Transfers
The AD9547 instruction word and payload can be MSB first or
LSB first. The default for the AD9547 is MSB first. The LSB-first
mode can be set by writing a 1 to Register 0x0000, Bit 6. Immedi-
ately after the LSB-first bit is set, subsequent serial control port
operations are LSB first.
When MSB-first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB-first mode, the serial control port internal address
generator decrements for each data byte of the multibyte
transfer cycle.
Table 32. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
SCLK
SCLK
SDIO
SDIO
SDO
CS
CS
Table 32
DON'T CARE
DON'T CARE
DON'T CARE
SCLK
SDIO
CS
DON'T CARE
R/W
).
DON'T CARE
DON'T CARE
I14
W1
W1
R/W
W0
16-BIT INSTRUCTION HEADER
W1
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W0
I13
W0
A12
t
S
R/W
A11 A10 A9 A8 A7
16-BIT INSTRUCTION HEADER
I12
A12
t
Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DS
W1
Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
Figure 52. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
W0
t
DH
I11
A11
t
HIGH
W
A12
A6 A5
t
LOW
, which indicates
A11
I10
A10
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
Table 30
A10
Rev. B | Page 52 of 104
I9
A9
A9
).
A1 A0
t
CLK
A8
I8
A8
D7 D6 D5 D4 D3
A7
REGISTER (N – 1) DATA
When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data trans-
fers in LSB-first format start with an instruction byte that includes
the register address of the least significant payload byte, followed
by multiple data bytes. The serial control port internal byte address
generator increments for each byte of the multibyte transfer cycle.
For multibyte MSB-first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x0000. For multibyte LSB-first I/O operations,
the serial control port register address increments from the starting
address toward Address 0x1FFF. Unused addresses are not skipped
during multibyte I/O operations; therefore, the user should
write the default value to a reserved register and 0s to unmapped
registers. Note that it is more efficient to issue a new write
command than to write the default value to more than two
consecutive reserved (or unmapped) registers.
Table 31. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB First
MSB First
REGISTER (N) DATA
I7
A7
A6
A5
I6
A6
D2 D1 D0 D7
D4
Address Direction
Increment
Decrement
I5
A5
REGISTER (N – 2) DATA
D3
I4
A4
D2
D6 D5
REGISTER (N – 1) DATA
D1
D4 D3 D2
I3
A3
D0
Stop Sequence
0x0000 ... 0x1FFF
0x1FFF ... 0x0000
REGISTER (N – 3) DATA
t
C
I2
A2
D1 D0
DON'T CARE
DON'T CARE
I1
A1
DON'T CARE
DON'T CARE
DON'T CARE
LSB
I0
A0
DON'T
CARE