EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 102

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Referenced Documents
Referenced
Documents
5–32Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 5–34. MAX II JTAG Timing Parameters (Part 2 of 2)
Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO will degrade the maximum
TCK frequency.
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the t
values at 35 ns.
Symbol
Table
5–34:
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
This chapter references the following documents:
■
■
■
■
■
■
■
I/O Structure section in the
Device Handbook
Hot Socketing and Power-On Reset in MAX II Devices
MAX II Device Handbook
Operating Requirements for Altera Devices Data Sheet
PowerPlay Power Analysis
Handbook
Understanding and Evaluating Power in MAX II Devices
MAX II Device Handbook
Understanding Timing in MAX II Devices
Handbook
Using MAX II Devices in Multi-Voltage Systems
Device Handbook
Parameter
(2)
JPSU
minimum is 6 ns and t
(2)
(2)
chapter in volume 3 of the Quartus II
MAX II Architecture
JPCO
Min
10
10
—
—
—
—
—
—
8
chapter in the MAX II Device
, t
JPZX
, and t
chapter in the MAX II
chapter in the MAX II
Max
JPXZ
15
15
15
25
25
25
—
—
—
Altera Corporation
chapter in the
are maximum
chapter in the
July 2008
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns