EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 29

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Altera Corporation
March 2008
control signals, such as clock enables, synchronous or asynchronous
clears, presets, output enables, or protocol control signals such as TRDY
and IRDY for PCI. Internal logic can drive the global clock network for
internally-generated global clocks and control signals.
the various sources that drive the global clock network.
Figure 2–13. Global Clock Generation
Note to
(1)
The global clock network drives to individual LAB column signals, LAB
column clocks [3..0], that span an entire LAB column from the top to the
bottom of the device. Unused global clocks or control signals in a LAB
column are turned off at the LAB column clock buffers shown in
Figure
LAB clock signals and one LAB clear signal. Other control signal types
route from the global clock network into the LAB local interconnect. See
“LAB Control Signals” on page 2–6
Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated
global clock signal.
2–14. The LAB column clocks [3..0] are multiplexed down to two
Figure 2–13
Logic Array(1)
GCLK0
GCLK1
GCLK2
GCLK3
:
4
for more information.
MAX II Device Handbook, Volume 1
4
Global Clock
Network
Figure 2–13
MAX II Architecture
shows
2–21