EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 16

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Logic Elements
Logic Elements
Figure 2–6. MAX II LE
2–8Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Reset (DEV_CLRn)
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
data1
data2
data3
data4
addnsub
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock and
LAB Carry-In
Select
Carry-In1
Carry-In0
The smallest unit of logic in the MAX II architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry-select capability. A
single LE also supports dynamic single-bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and
DirectLink interconnects. See
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any LE can drive the register’s clock and
clear control signals. Either general-purpose I/O pins or LEs can drive the
clock enable, preset, asynchronous load, and asynchronous data. The
Look-Up
Table
(LUT)
Chain
Carry
Register chain
routing from
previous LE
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Figure
Clear
2–6.
Register Bypass
Packed
Register Select
ADATA
D
ENA
PRN/ALD
CLRN
Register
Feedback
Q
Programmable
Register
Altera Corporation
LUT chain
routing to next LE
Row, column,
and DirectLink
routing
Row, column,
and DirectLink
routing
Local routing
Register chain
output
March 2008