EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 36

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

I/O Structure
Figure 2–18. MultiVolt Core Feature in MAX II Devices
I/O Structure
2–28Core Version a.b.c variable
MAX II Device Handbook, Volume 1
3.3-V or 2.5-V on
VCCINT Pins
IOEs support many features, including:
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MAX II device IOEs contain a bidirectional I/O buffer.
the MAX II IOE structure. Registers from adjacent LABs can drive to or be
driven from the IOE’s bidirectional I/O buffers. The Quartus II software
automatically attempts to place registers in the adjacent LAB with fast
I/O connection to achieve the fastest possible clock-to-output and
registered output enable timing. For input registers, the Quartus II
software automatically routes the register to guarantee zero hold time.
You can set timing assignments in the Quartus II software to achieve
desired I/O timing.
1.8-V Core
Regulator
Voltage
Voltage
LVTTL and LVCMOS I/O standards
3.3-V, 32-bit, 66-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system
programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
MAX II Device
VCCINT Pins
1.8-V on
1.8-V Core
MAX IIG or MAX IIZ Device
Voltage
Figure 2–19
Altera Corporation
March 2008
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