EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 51

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Introduction
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
Altera Corporation
December 2007
SAMPLE/PRELOAD
EXTEST
BYPASS
MII51003-1.5
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
(1)
Instruction Code
00 0000 0101
00 0000 1111
11 1111 1111
This chapter discusses how to use the IEEE Standard 1149.1
Boundary-Scan Test (BST) circuitry in MAX II devices and includes the
following sections:
■
■
All MAX
boundary-scan test (BST) circuitry that complies with the IEEE Std.
1149.1-2001 specification. JTAG boundary-scan testing can only be
performed at any time after V
powered and a t
also use the JTAG port for in-system programming together with either
the Quartus
(.pof), Jam
(.jam), or Jam Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard are determined by the V
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in
“IEEE Std. 1149.1 (JTAG) Boundary-Scan Support” on page 3–1
“In System Programmability” on page 3–5
®
TM
II devices provide Joint Test Action Group (JTAG)
®
Standard Test and Programming Language (STAPL) Files
II software or hardware using Programming Object Files
CONFIG
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation.
In-System Programmability
amount of time has passed. MAX II devices can
CCINT
Chapter 3. JTAG and
and all V
Description
CCIO
banks have been fully
Table
CCIO
3–1.
of the
3–1