EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 28

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Global Signals
Global Signals
2–20Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Note to
(1)
LUT Chain
Register
Chain
Local
Interconnect
DirectLink
Interconnect
R4
Interconnect
C4
Interconnect
LE
UFM Block
Column IOE
Row IOE
Table 2–2. MAX II Device Routing Scheme
Source
These categories are interconnects.
Table 2–2
Chain
LUT
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:
Register
Chain
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The UFM block communicates with the logic array similar to LAB-to-LAB
interfaces. The UFM block connects to row and column interconnects and
has local interconnect regions driven by row and column interconnects.
This block also has DirectLink interconnects for fast connections to and
from a neighboring LAB. For more information about the UFM interface
to the logic array, see
Table 2–2
Each MAX II device has four dual-purpose dedicated clock pins
(GCLK[3..0], two pins on the left side and two pins on the right side)
that drive the global clock network for clocking, as shown in
These four pins can also be used as general-purpose I/O if they are not
used to drive the global clock network.
The four global clock lines in the global clock network drive throughout
the entire device. The global clock network can provide clocks for all
resources within the device including LEs, LAB local interconnect, IOEs,
and the UFM block. The global clock lines can also be used for global
Local
(1)
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v
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shows the MAX II device routing scheme.
DirectLink
(1)
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R4
“User Flash Memory Block” on page
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v
v
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Destination
(1)
C4
v
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v
v
v
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(1)
LE
v
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v
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Block
UFM
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Column
IOE
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v
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Altera Corporation
2–23.
Row
IOE
Figure
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March 2008
Fast I/O
2–13.
(1)
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