EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 33

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Altera Corporation
March 2008
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Auto-Increment Addressing
The UFM block supports standard read or stream read operations. The
stream read is supported with an auto-increment address feature.
Deasserting the ARSHIFT signal while clocking the ARCLK signal
increments the address register value to read consecutive locations from
the UFM array.
Serial Interface
The UFM block supports a serial interface with serial address and data
signals. The internal shift registers within the UFM block for address and
data are 9 bits and 16 bits wide, respectively. The Quartus II software
automatically generates interface logic in LEs for a parallel address and
data interface to the UFM block. Other standard protocol interfaces such
as SPI are also automatically generated in LE logic by the Quartus II
software.
For more information about the UFM interface signals and the Quartus II
LE-based alternate interfaces, refer to the
MAX II Devices
UFM Block to Logic Array Interface
The UFM block is a small partition of the flash memory that contains the
CFM block, as shown in
EPM240 device is located on the left side of the device adjacent to the left
most LAB column. The UFM block for the EPM570, EPM1270, and
EPM2210 devices is located at the bottom left of the device. The UFM
input and output signals interface to all types of interconnects (R4
interconnect, C4 interconnect, and DirectLink interconnect to/from
adjacent LAB rows). The UFM signals can also be driven from global
clocks, GCLK[3..0]. The interface region for the EPM240 device is
shown in
EPM2210 devices are shown in
Figure
chapter in the MAX II Device Handbook.
2–16. The interface regions for EPM570, EPM1270, and
Figures 2–1
Figure
and 2–2. The UFM block for the
2–17.
MAX II Device Handbook, Volume 1
Using User Flash Memory in
MAX II Architecture
2–25