EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 66

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset
Circuitry
4–6
MAX II Device Handbook, Volume 1
I/O
MAX II devices have POR circuits to monitor V
levels during power-up. The POR circuit monitors these voltages,
triggering download from the non-volatile configuration flash memory
(CFM) block to the SRAM logic, maintaining tri-state of the I/O pins
(with weak pull-up resistors enabled) before and during this process.
When the MAX II device enters user mode, the POR circuit releases the
I/O pins to user functionality. The POR circuit of the MAX II (except
MAX IIZ) device continues to monitor the V
brown-out condition. The POR circuit of the MAX IIZ device does not
monitor the V
More details are provided in the following sub-sections.
Power-Up Characteristics
When power is applied to a MAX II device, the POR circuit monitors
V
1.55 V for MAX IIG and MAX IIZ devices. From this voltage reference,
SRAM download and entry into user mode takes 200 to 450 µs maximum,
depending on device density. This period of time is specified as t
the power-up timing section of the
chapter in the MAX II Device Handbook.
CCINT
and begins SRAM download at an approximate voltage of 1.7 V or
GND
Core Version a.b.c variable
Source
Drain
Drain
Source
CCINT
PMOS
NMOS
voltage level after the device enters into user mode.
Gate
Gate
P-Substrate
DC and Switching Characteristics
N+
N+
CCINT
D
S
GND
CCINT
I/O
G
voltage level to detect a
and V
Altera Corporation
December 2007
CCIO
CONFIG
voltage
in