EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 4

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Features
1–2
MAX II Device Handbook, Volume 1
Notes to
(1)
(2)
LEs
Typical Equivalent
Macrocells
Equivalent Macrocell
Range
UFM Size (bits)
Maximum User I/O pins
t
f
t
t
PD1
CNT
SU
CO
Table 1–1. MAX II Family Features
(ns)
(ns)
(ns)
(MHz)
t
combinational logic implemented in a single LUT and LAB that is adjacent to the output pin.
The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay
will run faster than this number.
PD1
Feature
(1)
represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and
Table
(2)
1–1:
f
128 to 240 240 to 570 570 to 1,270 1,270 to 2,210
EPM240G
EPM240
8,192
240
192
304
4.7
1.7
4.3
80
Table 1–1
For more information about equivalent macrocells, refer to the
Logic Element to Macrocell Conversion Methodology
MAX II and MAX IIG devices are available in three speed grades: –3, –4,
and –5, with –3 being the fastest. Similarly, MAX IIZ devices are available
in two speed grades: –6, –7, with –6 being faster. These speed grades
represent the overall relative performance, not any specific timing
parameter. For propagation delay timing numbers within each speed
grade and density, refer to the
the MAX II Device Handbook.
EPM570G
EPM570
8,192
Core Version a.b.c variable
shows the MAX II family features.
570
440
160
304
5.4
1.2
4.5
EPM1270G
EPM1270
1,270
8,192
980
212
304
6.2
1.2
4.6
DC and Switching Characteristics
EPM2210G
EPM2210
2,210
1,700
8,192
272
304
7.0
1.2
4.6
128 to 240
EPM240Z
white paper.
8,192
240
192
152
7.5
2.3
6.5
80
Altera Corporation
December 2007
240 to 570
EPM570Z
chapter in
MAX II
8,192
570
440
160
152
9.0
2.2
6.7