EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 42

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EPM2210GF256I5N

Manufacturer Part Number
EPM2210GF256I5N
Description
MAX II
Manufacturer
Altera
Datasheet

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I/O Structure
Figure 2–22. MAX II I/O Banks for EPM240 and EPM570
Notes to
(1)
(2)
2–34Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Figure 2–22
Figure 2–22
I/O Bank 1
Figure
2–22:
is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.
is a top view of the silicon die.
The EPM1270 and EPM2210 devices support four I/O banks, as shown in
Figure
standards shown in
supports the PCI clamping diode on inputs and PCI drive compliance on
outputs. You must use Bank 3 for designs requiring PCI compliant I/O
pins. The Quartus II software automatically places I/O pins in this bank
if assigned with the PCI I/O standard.
2–23. Each of these banks support all of the LVTTL and LVCMOS
All I/O Banks Support
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Table
2–4. PCI I/O is supported in Bank 3. Bank 3
Notes
(1),
(2)
Altera Corporation
I/O Bank 2
March 2008

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