EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 65

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EPM2210GF256I5N

Manufacturer Part Number
EPM2210GF256I5N
Description
MAX II
Manufacturer
Altera
Datasheet

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0
Figure 4–3. ESD Protection During Positive Voltage Zap
Altera Corporation
December 2007
I/O
When the I/O pin receives a negative ESD zap at the pin that is less than
–0.7 V (0.7 V is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge
ESD current path is from GND to the I/O pin, as shown in
GND
Source
Drain
Drain
Source
NMOS
PMOS
Hot Socketing and Power-On Reset in MAX II Devices
Gate
Gate
P-Substrate
MAX II Device Handbook, Volume 1
N+
N+
D
S
GND
I/O
G
Figure
4–4.
4–5

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