EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 63

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Hot Socketing
Feature
Implementation
in MAX II
Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices
Altera Corporation
December 2007
Resistor
Pull-Up
Weak
PAD
The DC specification applies when all VCC supplies to the device are
stable in the powered-up or powered-down conditions.
The hot socketing feature turns off (tri-states) the output buffer during the
power-up event (either V
The hot-socket circuit generates an internal HOTSCKT signal when either
V
power-down. The HOTSCKT signal cuts off the output buffer to make sure
that no DC current (except for weak pull-up leaking) leaks through the
pin. When V
relatively low even after the power-on reset (POR) signal is released and
device configuration is complete.
1
Each I/O and clock pin has the circuitry shown in
The POR circuit monitors V
pins tri-stated until the device has completed its flash memory
configuration of the SRAM logic. The weak pull-up resistor (R) from the
I/O pin to V
floating. The 3.3-V tolerance control circuit permits the I/O pins to be
CCINT
or V
V
Make sure that the V
range even though SRAM download has completed.
CCIO
CCIO
CC
CCIO
ramps up very slowly during power-up, V
is below the threshold voltage during power-up or
is enabled during download to keep the I/O pins from
Hot Socketing and Power-On Reset in MAX II Devices
Input Buffer
to Logic Array
CCINT
Tolerance
Voltage
Control
CCINT
CCINT
or V
and V
Output Enable
is within the recommended operating
CCIO
CCIO
MAX II Device Handbook, Volume 1
supplies) or power-down event.
voltage levels and keeps I/O
Hot Socket
Power On
Monitor
Reset
Figure
4–1.
CC
may still be
4–3