EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 9

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Introduction
Functional
Description
Altera Corporation
March 2008
MII51002-2.1
This chapter describes the architecture of the MAX II device and contains
the following sections:
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MAX
architecture to implement custom logic. Row and column interconnects
provide signal interconnects between the logic array blocks (LABs).
The logic array consists of LABs, with 10 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device. The MultiTrack interconnect provides fast granular timing delays
between LABs. The fast routing between LEs provides minimum timing
delay for added levels of logic versus globally routed interconnect
structures.
The MAX II device I/O pins are fed by I/O elements (IOE) located at the
ends of LAB rows and columns around the periphery of the device. Each
IOE contains a bidirectional I/O buffer with several advanced features.
I/O pins support Schmitt trigger inputs and various single-ended
standards, such as 66-MHz, 32-bit PCI, and LVTTL.
MAX II devices provide a global clock network. The global clock network
consists of four global clock lines that drive throughout the entire device,
providing clocks for all resources within the device. The global clock lines
can also be used for control signals such as clear, preset, or output enable.
Figure 2–1
“Functional Description” on page 2–1
“Logic Array Blocks” on page 2–5
“Logic Elements” on page 2–8
“MultiTrack Interconnect” on page 2–15
“Global Signals” on page 2–20
“User Flash Memory Block” on page 2–23
“MultiVolt Core” on page 2–27
“I/O Structure” on page 2–28
®
II devices contain a two-dimensional row- and column-based
Core Version a.b.c variable
shows a functional block diagram of the MAX II device.
Chapter 2. MAX II
Architecture
2–1