EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 64

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Hot Socketing Feature Implementation in MAX II Devices
Figure 4–2. Transistor-Level Diagram of MAX II Device I/O Buffers
4–4
MAX II Device Handbook, Volume 1
n+
f
IOE Signal
p - well
driven by 3.3 V before V
the I/O pins from driving out when the device is not fully powered or
operational. The hot socket circuit prevents I/O pins from internally
powering V
device is powered.
For information about 5.0-V tolerance, refer to the
in Multi-Voltage Systems
Figure 4–2
buffers. This design ensures that the output buffers do not drive when
V
V
The V
The CMOS output drivers in the I/O pins intrinsically provide
electrostatic discharge (ESD) protection. There are two cases to consider
for ESD voltage strikes: positive voltage zap and negative voltage zap.
A positive ESD voltage zap occurs when a positive voltage is present on
an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/
P-Substrate junction of the N-channel drain to break down and the N+
(Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turn on to
discharge ESD current from I/O pin to GND. The dashed line (see
Figure
zap.
n+
CCIO
CCIO
. This also applies for sudden voltage spikes during hot insertion.
PAD
is powered before V
4–3) shows the ESD current discharge path during a positive ESD
VPAD
leakage current charges the 3.3-V tolerant circuit capacitance.
Core Version a.b.c variable
shows a transistor-level cross section of the MAX II device I/O
CCIO
and V
Larger of VCCIO or VPAD
p+
CCINT
IOE Signal or the
CCIO
chapter in the MAX II Device Handbook.
CCINT
when driven by external signals before the
and/or V
n - well
or if the I/O pad voltage is higher than
VCCIO
CCINT
p+
p - substrate
VCCIO or VPAD
The Larger of
are powered, and it prevents
n+
Using MAX II Devices
Altera Corporation
December 2007
Ensures 3.3-V
Tolerance and
Hot-Socket
Protection