EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 56

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

In System Programmability
3–6
MAX II Device Handbook, Volume 1
f
programming, the I/O pins are tri-stated and weakly pulled-up to V
to eliminate board conflicts. The in-system programming clamp and real-
time ISP feature allow user control of I/O state or behavior during ISP.
For more information, refer to
page 3–8
These devices also offer an ISP_DONE bit that provides safe operation
when in-system programming is interrupted. This ISP_DONE bit, which
is the last bit programmed, prevents all I/O pins from driving until the
bit is programmed.
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant
to the IEEE 1532-2002 programming specification. This provides
industry-standard hardware and software for in-system programming
among multiple vendor programmable logic devices (PLDs) in a JTAG
chain.
The MAX II 1532 BSDL files will be released on the Altera website when
available.
Jam Standard Test and Programming Language (STAPL)
The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II
devices with in-circuit testers, PCs, or embedded processors. The Jam
byte code is also supported for MAX II devices. These software
programming protocols provide a compact embedded solution for
programming MAX II devices.
For more information, refer to the
Embedded Processor
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data
are shifted into the MAX II device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data. Programming a pattern into the device requires the
following six ISP steps. A stand-alone verification of a programmed
pattern involves only stages 1, 2, 5, and 6. These steps are automatically
executed by third-party programmers, the Quartus II software, or the Jam
STAPL and Jam Byte-Code Players.
1.
Enter ISP—The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode.
Core Version a.b.c variable
and
“Real-Time ISP” on page
chapter in the MAX II Device Handbook.
“In-System Programming Clamp” on
Using Jam STAPL for ISP via an
3–8.
Altera Corporation
December 2007
CCIO