EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 19

• Manufacturer Part Number: EPM2210GF256I5N
• Description: MAX II
• Manufacturer: Altera

Figure 2–7. LE in Normal Mode
Note to
(1)
Altera Corporation
March 2008
addnsub (LAB Wide)
data1
data2
data3
cin (from cout
of previous LE)
data4
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
Figure
(1)
2–7:
Register Feedback
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic
arithmetic mode uses four 2-input LUTs configurable as a dynamic
adder/subtractor. The first two 2-input LUTs compute two summations
based on a possible carry-in of 1 or 0; the other two LUTs generate carry
outputs for the two chains of the carry-select circuitry. As shown in
Figure
carry-in1 chain. The selected chain’s logic level in turn determines
which parallel sum is generated as a combinational or registered output.
For example, when implementing an adder, the sum output is the
selection of two possible calculated sums:
data1 + data2 + carry in0
or
data1 + data2 + carry-in1
4-Input
LUT
2–8, the LAB carry-in signal selects either the carry-in0 or
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
(LAB Wide)
ADATA
ENA
D
MAX II Device Handbook, Volume 1
ALD/PRE
aload
CLRN
Q
MAX II Architecture
Row, column, and
DirectLink routing
Row, column, and
DirectLink routing
Local routing
LUT chain
connection
Register
chain output
2–11