LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 108

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LAN9311-NZW

Manufacturer Part Number
LAN9311-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9311-NZW

Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 1.7 (06-29-10)
8.5.5
D[15:0] (OUTPUT)
END_SEL
nCS, nRD
A[x:5]
A[4:1]
PIO Burst Reads
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read
begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert
between bursts for the period specified in
page
asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram
in
Note: A[1] must toggle during burst reads. Fresh data is supplied each time A[1] is toggled.
The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.
Please refer to
specifications for PIO burst read operations.
Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are
Figure
448. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be
not supported.
8.4.
Figure 8.4 Functional Timing for PIO Burst Read Operation
Section 15.5.5, "PIO Burst Read Cycle Timing," on page 448
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108
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Table 15.9, “PIO Burst Read Cycle Timing Values,” on
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SMSC LAN9311/LAN9311i
for the AC timing
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Datasheet

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