LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 245

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.7.2
31:16
15:11
BITS
10:6
5:2
1
0
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to
"PHY Addressing," on page 82
assignments.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to
"Ethernet PHY Control and Status Registers," on page 287
descriptions on all PHY registers.
RESERVED
RESERVED
Note:
RESERVED
PHY Management Interface Access Register (PMI_ACCESS)
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the
Register (PMI_DATA)
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to
This bit must always be written with a value of 1.
Section 10.2.4, "EEPROM Loader," on page 150
Offset:
to perform write operations to the PHYs.
0A8h
EEPROM Loader
Access Only
DESCRIPTION
for information on PHY address
DATASHEET
245
Size:
for additional information.
for detailed
Section 7.1.1,
Section 14.4,
32 bits
PHY Management Interface Data
TYPE
WO
WO
WO
RO
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
00000b
00000b
0b
0b
-
-