LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 263

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
19:16
15:14
13:12
BITS
11:1
0
TX FIFO Size (TX_FIF_SZ)
This field sets the size of the TX FIFOs in 1KB values to a maximum of
14KB. The TX Status FIFO consumes 512 bytes of the space allocated by
TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space
specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX
Data FIFO and Status FIFO combined). The TX Data FIFO is used for both
TX data and TX commands.
The RX Status and Data FIFOs consume the remaining space, which is
equal to 16KB minus TX_FIF_SIZ. See section
Memory Allocation Configuration," on page 122
RESERVED
RESERVED - This field must be written with 00b for proper operation.
RESERVED
Soft Reset (SRST)
Writing 1 generates a software initiated reset to the Host Bus Interface, the
Host MAC, and System CSR’s below address 100h. The System CSR’s are
all reset except for any NASR bits. Soft reset also clears any TX or RX
errors in the Host MAC transmitter and receiver (TXE/RXE). This bit is self-
clearing. In order to reset all values, the
(RESET_CTL)
Note:
Note 14.47 The default value of this field is determined by the configuration strap auto_mdix_strap_2.
Note 14.48 The default value of this field is determined by the configuration strap auto_mdix_strap_1.
This bit will read high during assertion of DIGITAL_RST in the
Reset Control Register
must always be read at least once after power-up or reset to
ensure that write operations function correctly.
See
See
must be used.
Section 4.2.4, "Configuration Straps," on page 40
Section 4.2.4, "Configuration Straps," on page 40
DESCRIPTION
(RESET_CTL). The LAN9311/LAN9311i
DATASHEET
Reset Control Register
263
Section 9.7.3, "FIFO
for more information.
for more information.
for more information.
TYPE
R/W
R/W
R/W
RO
RO
SC
Revision 1.7 (06-29-10)
DEFAULT
00b
5h
0b
-
-