LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 45

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
4.2.4.2
STRAP NAME
manual_FC_strap_2
BP_EN_strap_mii
FD_FC_strap_mii
manual_FC_strap_mii
SQE_test_disable_strap_mii
Hard-Straps
Hard-straps are latched upon Power-On Reset (POR) or pin reset (nRST) only. Unlike soft-straps,
hard-straps always have an associated pin and cannot be overridden by the EEPROM Loader. These
straps are used as either direct configuration values or as register defaults.
all hard-straps and their associated pin. These straps, along with their pin assignments are also fully
defined in
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
Chapter 3, "Pin Description and Configuration," on page
DESCRIPTION
Port 2 Manual Flow Control Enable Strap: Configures the
default value of the
Select (MANUAL_FC_2)
Control Register
flow control is determined by auto-negotiation (if enabled),
and symmetric PAUSE is advertised (bit 10 of the
PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
When configured high, flow control is determined by the
Port 2 Full-Duplex Transmit Flow Control Enable
(TX_FC_2)
Enable (RX_FC_2)
advertised (bit 10 of the
Advertisement Register (PHY_AN_ADV_x)
Port 0(Host MAC) Backpressure Enable Strap:
Configures the default value for the
Enable (BP_EN_MII)
Flow Control Register
configured low, backpressure is disabled. When configured
high, backpressure is enabled.
Port 0(Host MAC) Full-Duplex Flow Control Enable
Strap: Configures the default of the TX_FC_MII and
RX_FC_MII bits in the
Control Register (MANUAL_FC_MII)
manual full-duplex flow control is selected. When
configured low, flow control is disabled on RX/TX. When
configured high, flow control is enabled on RX/TX.
Port 0(Host MAC) Manual Flow Control Enable Strap:
Configures the default value of the MANUAL_FC_MII bit in
the
(MANUAL_FC_MII). When configured low, flow control is
determined by Virtual Auto-Negotiation (if enabled). When
configured high, flow control is determined by TX_FC_MII
and RX_FC_MII bits in the
Control Register
SQE Heartbeat Disable Strap: Configures the Signal
Quality Error (Heartbeat) test function by controlling the
default value of the SQEOFF (bit 0) of the
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS). When configured
low, SQEOFF defaults to 0 and SQE test is enabled. When
configured high, SQEOFF defaults to 1 and SQE test is
disabled.
Port 0(Host MAC) Manual Flow Control Register
and
DATASHEET
Port 2 Full-Duplex Receive Flow Control
(MANUAL_FC_2). When configured low,
(MANUAL_FC_MII).
is set).
Port 2 Full-Duplex Manual Flow Control
bits, and symmetric PAUSE is not
bit of the
(MANUAL_FC_MII). When
Port 0(Host MAC) Manual Flow
45
Port x PHY Auto-Negotiation
bit in the
Port 0(Host MAC) Manual Flow
Port 0(Host MAC) Manual
Port 2 Manual Flow
Port 0 Backpressure
which are used when
is cleared).
Virtual PHY
26.
Port x
Table 4.3
PIN / DEFAULT
VALUE
0b
1b
1b
0b
0b
Revision 1.7 (06-29-10)
provides a list of