LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 29

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
114,117
83-86
PIN
127
126
124
123
PIN
119
Note 3.1
Note 3.2
Analog Power
+3.3V Port 1
Ethernet RX
Ethernet RX
Purpose I/O
Ethernet TX
Ethernet TX
Port 2 LED
Reference
Indicators
Negative
Negative
General
Positive
Positive
Supply
NAME
NAME
Port 2
Port 2
Port 2
Port 2
Data
Bias
The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected or manually selected, the RX and TX pins
will be swapped internally.
The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected or manually selected, the RX and TX pins
will be swapped internally.
Table 3.3 LAN Port 1 & 2 Power and Common Pins
nP2LED[3:0]
GPIO[7:4]
VDD33A1
SYMBOL
SYMBOL
EXRES
TXN2
RXN2
RXP2
TXP2
Table 3.2 LAN Port 2 Pins
DATASHEET
BUFFER
BUFFER
IS/O12/
TYPE
OD12
OD12
TYPE
(PU)
AIO
AIO
AIO
AIO
AI
P
29
LED indicators: When configured as LED outputs
via the
these pins are open-drain, active low outputs and
the pull-ups and input buffers are disabled. The
functionality of each pin is determined via the
LED_CFG[9:8] bits.
General Purpose I/O Data: When configured as
GPIO via the
(LED_CFG), these general purpose signals are
fully programmable as either push-pull outputs,
open-drain outputs or Schmitt-triggered inputs by
writing the
Register (GPIO_CFG)
Data & Direction Register
pull-ups are enabled in GPIO mode. The input
buffers are disabled when set as an output.
Note:
Ethernet TX Negative: Negative output of Port 2
Ethernet transmitter. See
information.
Ethernet TX Positive: Positive output of Port 2
Ethernet transmitter. See
information.
Ethernet RX Negative: Negative input of Port 2
Ethernet receiver. See
information.
Ethernet RX Positive: Positive input of Port 2
Ethernet receiver. See
information.
Bias Reference: Used for internal bias circuits.
Connect to an external 12.4K ohm, 1% resistor to
ground.
+3.3V Port 1 Analog Power Supply
Refer to the LAN9311/LAN9311i application note
for additional connection information.
LED Configuration Register
See
on page 163
General Purpose I/O Configuration
LED Configuration Register
Chapter 13, "GPIO/LED Controller,"
DESCRIPTION
DESCRIPTION
for additional details.
and
Note 3.2
Note 3.2
Note 3.2
Note 3.2
(GPIO_DATA_DIR). The
General Purpose I/O
Revision 1.7 (06-29-10)
for additional
for additional
for additional
for additional
(LED_CFG),