LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 250

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
BITS
6
5
4
3
2
1
0
MF Preamble Suppression
This bit indicates whether the Virtual PHY accepts management frames with
the preamble suppressed.
0: Management frames with preamble suppressed not accepted
1: Management frames with preamble suppressed accepted
Auto-Negotiation Complete
This bit indicates the status of the Auto-Negotiation process.
0: Auto-Negotiation process not completed
1: Auto-Negotiation process completed
Remote Fault
This bit indicates if a remote fault condition has been detected.
0: No remote fault condition detected
1: Remote fault condition detected
Auto-Negotiation Ability
This bit indicates the status of the Virtual PHY’s auto-negotiation.
0: Virtual PHY is unable to perform auto-negotiation
1: Virtual PHY is able to perform auto-negotiation
Link Status
This bit indicates the status of the link.
0: Link is down
1: Link is up
Jabber Detect
This bit indicates the status of the jabber condition.
0: No jabber condition detected
1: Jabber condition detected
Extended Capability
This bit indicates whether extended register capability is supported.
0: Basic register set capabilities only
1: Extended register set capabilities
Note 14.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.18 The Virtual PHY supports 100BASE-X (half and full duplex) and 10BASE-T (half and full
Note 14.19 The Virtual PHY does not support Register 15 or 1000 Mb/s operation. Thus this bit is
Note 14.20 The Auto-Negotiation Complete bit is first cleared on a reset, but set shortly after (when
Note 14.21 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber.
Note 14.22 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
duplex) only. All other modes will always return as 0 (unable to perform).
always returned as 0.
the Auto-Negotiation process is run). Refer to
Negotiation," on page 96
supports Registers 0-6 (per the IEEE 802.3 specification).
DESCRIPTION
DATASHEET
for additional details.
250
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Section 7.3.1, "Virtual PHY Auto-
TYPE
SMSC LAN9311/LAN9311i
RO
RO
RO
RO
RO
RO
RO
Note 14.20
Note 14.21
Note 14.21
Note 14.21
Note 14.22
DEFAULT
Datasheet
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1b
0b
1b
1b
0b
1b