LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 159

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
11.2.2
PTP ADDRESS
User Defined
(Alternate 1)
(Alternate 2)
(Alternate 3)
224.0.1.129
224.0.1.130
224.0.1.131
224.0.1.132
(Primary)
PTP Message Detection
In order to provide the most flexibility, loose packet type matching is used by the LAN9311/LAN9311i.
This assumes that for all packets received with a valid FCS, only the MAC destination address is
required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in
the PTP protocol: 224.0.1.129 through 224.0.1.132. These map to Ethernet MAC addresses
01:00:5e:00:01:81 through 01:00:5e:00:01:84. Each of these addresses has one enable bit per port in
the
as a PTP address on the specified port.
In addition to the fixed addresses, a user defined (host programmable) PTP address may be input via
the
Address Low-DWORD Register
disabled/enabled as a PTP address on each port via the dedicated enable bits in the
Configuration Register
corresponding enable bits can be seen in
Once a packet is determined to match a PTP destination address, it is further qualified as a Sync or
Delay_Req message type. On Ethernet, PTP uses UDP messages. Within the UDP payload is the PTP
control byte (offset 32 starting at 0). This byte determines the message type: 0x00 for a Sync message,
0x01 for a Delay_Req message. The UDP payload starts at packet byte offset 42 (from 0) for untagged
packets and at byte offset 46 for tagged packets.
Note: Both tagged and untagged packets are supported. Only Ethernet II packet encoding and IPv4
Note: For proper routing of the PTP packets, the host must program an entry into the switch engine
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)
1588 Configuration Register (1588_CONFIG)
are supported.
Address Logic Resolution (ALR) Table. The MAC address should be one of the reserved
Multicast addresses in
bits must also be set. Refer to
(1588_CONFIG). A summary of the supported PTP multicast addresses and
1588_AUX_MAC_LO registers)
Table 11.3 PTP Multicast Addresses
(1588_AUX_MAC_HI &
User Defined Address
CORRESPONDING
01:00:5e:00:01:81
01:00:5e:00:01:82
01:00:5e:00:01:83
01:00:5e:00:01:84
Table
MAC ADDRESS
DATASHEET
(1588_AUX_MAC_LO). The user defined address may be
11.3, with Port 0(Host MAC) as a destination.The Static and Valid
Chapter 6, "Switch Fabric," on page 55
159
Table
11.3.
which enables/disables the corresponding address
RELATED ENABLE BITS IN THE
MAC_USER_EN_MII (Port 0)
MAC_ALT1_EN_MII (Port 0)
MAC_ALT2_EN_MII (Port 0)
MAC_ALT3_EN_MII (Port 0)
MAC_USER_EN_1 (Port 1)
MAC_USER_EN_2 (Port 2)
1588_CONFIG REGISTER
MAC_PRI_EN_MII (Port 0)
MAC_ALT1_EN_1 (Port 1)
MAC_ALT1_EN_2 (Port 2)
MAC_ALT2_EN_1 (Port 1)
MAC_ALT2_EN_2 (Port 2)
MAC_ALT3_EN_1 (Port 1)
MAC_ALT3_EN_2 (Port 2)
MAC_PRI_EN_1 (Port 1)
MAC_PRI_EN_2 (Port 2)
and
for more information.
Revision 1.7 (06-29-10)
1588 Auxiliary MAC
1588