LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 175

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.1.2
BITS
31
30
29
28
27
26
25
24
23
22
21
20
Software Interrupt (SW_INT)
This interrupt is generated when the SW_INT_EN bit of the
Register (INT_EN)
Device Ready (READY)
This interrupt indicates that the LAN9311/LAN9311i is ready to be accessed
after a power-up or reset condition.
1588 Interrupt Event (1588_EVNT)
This bit indicates an interrupt event from the IEEE 1588 module. This bit
should be used in conjunction with the
Register (1588_INT_STS_EN)
event within the 1588 module.
Switch Fabric Interrupt Event (SWITCH_INT)
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the
(SW_IPR)
Fabric.
Port 2 PHY Interrupt Event (PHY_INT2)
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the
Flags Register
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the
Flags Register
TX Stopped (TXSTOP_INT)
This interrupt is issued when STOP_TX bit in
Register (TX_CFG)
RX Stopped (RXSTOP_INT)
T
RX Dropped Frame Counter Halfway (RXDFH_INT)
This interrupt is issued when the
Register (RX_DROP)
80000000h).
RESERVED
TX IOC Interrupt (TX_IOC)
This interrupt is generated when a buffer with the IOC flag set has been
fully loaded into the TX Data FIFO.
RX DMA Interrupt (RXD_INT)
This interrupt is issued when the amount of data programmed in the RX
DMA Count (RX_DMA_CNT) field of the
(RX_CFG)
his interrupt is issued when the Host MAC receiver is halted.
Interrupt Status Register (INT_STS)
This register contains the current status of the generated interrupts. A value of 1 indicates the
corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions
have not been met. The bits of this register reflect the status of the interrupt source regardless of
whether the source has been enabled as an interrupt in the
indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
to determine the source of the interrupt event within the Switch
Offset:
has been transferred out of the RX Data FIFO.
(PHY_INTERRUPT_SOURCE_x).
(PHY_INTERRUPT_SOURCE_x).
is set high. Writing a one clears this interrupt.
is set, and the Host MAC transmitter is halted.
counts past its halfway point (7FFFFFFFh to
058h
DESCRIPTION
to determine the source of the interrupt
Switch Global Interrupt Pending Register
Host MAC RX Dropped Frames Counter
DATASHEET
1588 Interrupt Status and Enable
Receive Configuration Register
Port x PHY Interrupt Source
Port x PHY Interrupt Source
175
Transmit Configuration
Size:
Interrupt Enable
Interrupt Enable Register
32 bits
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
RO
RO
RO
Revision 1.7 (06-29-10)
(INT_EN). Where
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
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