LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 279

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.3.6
31:16
15:11
BITS
10:6
5:2
1
0
RESERVED
PHY Address (PHY_ADDR)
This field must be loaded with the PHY address that the MII access is
intended for. A list default PHY addresses can be seen in
to
PHY addressing.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY.
RESERVED
MII Write (MIIWnR)
Setting this bit tells the PHY that this will be a write operation using the
MAC MII Data Register
operation will occur, packing the data in the
(HMAC_MII_DATA).
MII Busy (MIIBZY)
This bit must be polled to determine when the MII register access is
complete. This bit must read a logical 0 before writing to this register or the
Host MAC MII Data Register
The LAN driver software must set this bit in order for the
LAN9311/LAN9311i to read or write any of the MII PHY registers.
During a MII register access, this bit will be set, signifying a read or write
access is in progress. The MII data register must be kept valid until the Host
MAC clears this bit during a PHY write operation. The MII data register is
invalid until the Host MAC has cleared this bit during a PHY read operation.
Section 7.1.1, "PHY Addressing," on page 82
Host MAC MII Access Register (HMAC_MII_ACC)
This read/write register is used in conjunction with the
to access the internal PHY registers. Refer to
Registers"
Offset:
for a list of accessible PHY registers and PHY address information.
(HMAC_MII_DATA). If this bit is cleared, a read
6h
(HMAC_MII_DATA).
DESCRIPTION
DATASHEET
Host MAC MII Data Register
279
for additional information on
Size:
Section 14.4, "Ethernet PHY Control and Status
Host MAC MII Data Register (HMAC_MII_DATA)
Table
7.1. Refer
32 bits
Host
TYPE
R/W
R/W
R/W
RO
RO
RO
SC
Revision 1.7 (06-29-10)
DEFAULT
00000b
00000b
0b
0b
-
-