LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 256

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
No Flow Control Enabled
Symmetric Pause
Asymmetric Pause Towards
Switch
Asymmetric Pause Towards MAC
BITS
4:0
7
6
5
100BASE-X Half Duplex
This bit indicates the emulated link partner PHY 100BASE-X half duplex
capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
10BASE-T Full Duplex
This bit indicates the emulated link partner PHY 10BASE-T full duplex
capability.
0: 10BASE-T full duplex ability not supported
1: 10BASE-T full duplex ability supported
10BASE-T Half Duplex
This bit indicates the emulated link partner PHY 10BASE-T half duplex
capability.
0: 10BASE-T half duplex ability not supported
1: 10BASE-T half duplex ability supported
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 14.33 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.34 The emulated link partner does not support next page, always instantly sends its link code
Note 14.35 The emulated link partner’s asymmetric/symmetric pause ability is based upon the values
Note 14.36 The emulated link partner always has the following capabilities: 100BASE-X full duplex,
Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
word, never sends a fault, and does not support 100BASE-T4.
of the
Advertisement Register
accommodates the request of the Virtual PHY, as shown in
"Virtual PHY Auto-Negotiation," on page 96
100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half duplex. For more
information on the Virtual PHY auto-negotiation, see
Negotiation," on page
Asymmetric Pause
VPHY Symmetric
(register 4.10)
Pause
DESCRIPTION
0
1
0
1
96.
DATASHEET
(VPHY_AN_ADV). Thus the emulated link partner always
VPHY Asymmetric
and
256
(register 4.11)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Pause
Pause
0
0
1
1
bits of the
for additional information.
Symmetric Pause
(register 5.10)
Link Partner
Section 7.3.1, "Virtual PHY Auto-
Virtual PHY Auto-Negotiation
0
1
1
0
Table
TYPE
14.5. See
SMSC LAN9311/LAN9311i
RO
RO
RO
RO
Asymmetric Pause
(register 5.11)
Link Partner
Section 7.3.1,
Note 14.36
Note 14.36
Note 14.36
DEFAULT
00001b
0
0
1
1
Datasheet