LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 43

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
STRAP NAME
manual_FC_strap_1
auto_mdix_strap_2
manual_mdix_strap_2
autoneg_strap_2
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 1 Manual Flow Control Enable Strap: Configures the
default value of the
Select (MANUAL_FC_1)
Control Register
flow control is determined by auto-negotiation (if enabled),
and symmetric PAUSE is advertised (bit 10 of the
PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
When configured high, flow control is determined by the
Port 1 Full-Duplex Transmit Flow Control Enable
(TX_FC_1)
Enable (RX_FC_1)
advertised (bit 10 of the
Advertisement Register (PHY_AN_ADV_x)
Port 2 Auto-MDIX Enable Strap: Configures the default
value for the Auto-MDIX functionality on Port 2 when the
AMDIXCTL bit in the
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
When configured low, Auto-MDIX is disabled. When
configured high, Auto-MDIX is enabled.
Note:
Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 2 when the auto_mdix_strap_2 is low and the
AMDIXCTL bit of the
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
Port 2 Auto Negotiation Enable Strap: Configures the
default value for the
in the PHY_BASIC_CTRL_2 register (See
Section
disabled. When configured high, auto-negotiation is
enabled.
This strap also affects the default value of the following bits:
Refer to the respective register definition sections for
additional information.
PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the
Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the
(PHY_SPECIAL_MODES_x)
14.4.2.1). When configured low, auto-negotiation is
If AMDIXCTL is set, this strap had no effect.
and
DATASHEET
Port 1 Full-Duplex Receive Flow Control
(MANUAL_FC_1). When configured low,
is set).
Port x PHY Auto-Negotiation
Port 1 Full-Duplex Manual Flow Control
bits, and symmetric PAUSE is not
Auto-Negotiation (PHY_AN)
Port x PHY Special Control/Status
Port x PHY Special Control/Status
Port x PHY Special Modes Register
43
Port x PHY Auto-Negotiation
bit in the
Port 1 Manual Flow
is cleared).
is cleared.
is cleared.
enable bit
Port x
PIN / DEFAULT
VALUE
0b
AUTO_MDIX_2
0b
1b
Revision 1.7 (06-29-10)