82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet
82P2284BB
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Quad T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2284 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 Version 6 February 25, 2008 Printed in U.S.A. © 2008 Integrated Device Technology, ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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TABLE OF CONTENTS ........................................................................................................................................................... 3 LIST OF TABLES .................................................................................................................................................................... 7 LIST OF FIGURES ................................................................................................................................................................... 9 FEATURES ............................................................................................................................................................................ 11 APPLICATIONS ..................................................................................................................................................................... 11 BLOCK DIAGRAM ................................................................................................................................................................ 12 1 PIN ASSIGNMENT .......................................................................................................................................................... 13 2 PIN DESCRIPTION ......................................................................................................................................................... 14 3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 22 ...
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IDT82P2284 3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) .............................................................................................................................. 64 3.13 INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ........................................................................................................................... 64 3.14 ELASTIC STORE BUFFER .......................................................................................................................................................................... 65 3.15 RECEIVE CAS/RBS BUFFER ..................................................................................................................................................................... 65 3.15.1 T1/J1 Mode ...................................................................................................................................................................................... 65 3.15.2 E1 Mode .......................................................................................................................................................................................... 66 ...
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IDT82P2284 3.24 WAVEFORM SHAPER / LINE BUILD OUT ............................................................................................................................................... 101 3.24.1 Preset Waveform Template ......................................................................................................................................................... 101 3.24.1.1 T1/J1 Mode .................................................................................................................................................................... 101 3.24.1.2 E1 Mode ......................................................................................................................................................................... 102 3.24.2 Line Build Out (LBO) (T1 Only) ................................................................................................................................................... 102 3.24.3 User-Programmable Arbitrary Waveform .................................................................................................................................. ...
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IDT82P2284 7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 347 7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 347 7.2 RECOMMENDED OPERATING CONDITIONS ......................................................................................................................................... 347 7.3 D.C. CHARACTERISTICS ......................................................................................................................................................................... 348 7.4 DIGITAL I/O TIMING CHARACTERISTICS ............................................................................................................................................... 349 7.5 CLOCK FREQUENCY REQUIREMENT .................................................................................................................................................... 349 7.6 T1/J1 ...
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Table 1: Operating Mode Selection ........................................................................................................................................................................... 23 Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 23 Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 24 Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 26 Table ...
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IDT82P2284 Table 49: Interrupt Summary In E1 Mode .................................................................................................................................................................... 93 Table 50: Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 93 Table 51: Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 95 Table 52: Related Bit / Register In Chapter ...
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Figure 1. 208-Pin PBGA (Top View) ........................................................................................................................................................................... 13 Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 24 Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 25 Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 25 Figure 5. Receive Path Monitoring ...
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IDT82P2284 Figure 49. Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... 359 Figure 50. Intel Non-Multiplexed Mode Read Cycle .................................................................................................................................................. 360 Figure 51. Intel Non-Multiplexed Mode Write Cycle .................................................................................................................................................. 361 Figure 52. SPI Timing Diagram ................................................................................................................................................................................. 362 List of Figures QUAD T1/E1/J1 ...
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... ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1) • Supports Analog Loopback, Digital Loopback and Remote Loop- back • Each receiver and transmitter can be individually powered down FRAMER • Each link can be configured as T1 • Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY- 000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704) and un-framed mode • ...
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IDT82P2284 BLOCK DIAGRAM Block Diagram QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 12 REFB_OUT REFA_OUT CLK_SEL[2:0] OSCO OSCI CLK_GEN_1.544 CLK_GEN_2.048 GPIO[1:0] RESET THZ A[9:0] D[7:1] D[0]/SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT TDO TDI TMS TCK TRST February ...
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IDT82P2284 1 PIN ASSIGNMENT TTIP4 TRING4 VDDAT4 VDDAR4 B NC VDDAX4 GNDA RTIP4 GNDA RRING4 GNDA GNDA E TSIG2 MTSIGB1 F TSIG1/ TSD2/ TSD4 TSIG4 MTSIGA1 MTSDB1 G ...
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IDT82P2284 2 PIN DESCRIPTION Name Type Pin No. RTIP[1] Input RTIP[2] RTIP[3] RTIP[4] RRING[1] RRING[2] RRING[3] RRING[4] TTIP[1] Output TTIP[2] TTIP[3] TTIP[4] TRING[1] TRING[2] TRING[3] TRING[4] RSD[1] / MRSDA[1] High-Z RSD[2] / MRSDB[1] Output RSD[3] RSD[4] RSIG[1] / MRSIGA[1] High-Z ...
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IDT82P2284 Name Type Pin No. RSFS[1] / MRSFS Output / Input RSFS[2] RSFS[3] RSFS[4] RSCK[1] / MRSCK Output / Input RSCK[2] RSCK[3] RSCK[4] TSD[1] / MTSDA[1] Input TSD[2] / MTSDB[1] TSD[3] TSD[4] Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT ...
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IDT82P2284 Name Type Pin No. TSIG[1] / MTSIGA[1] Input TSIG[2] / MTSIGB[1] TSIG[3] TSIG[4] TSFS[1] / MTSFS Output / Input TSFS[2] TSFS[3] TSFS[4] TSCK[1] / MTSCK Output / Input TSCK[2] TSCK[3] TSCK[4] Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT ...
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IDT82P2284 Name Type Pin No. OSCI Input OSCO Output CLK_SEL[0] Input CLK_SEL[1] CLK_SEL[2] CLK_GEN_1.544 Output CLK_GEN_2.048 Output REFA_OUT Output REFB_OUT Output RESET Input GPIO[0] Output / Input GPIO[1] THZ Input Note: * This feature is available in ZB revision only. ...
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IDT82P2284 Name Type Pin No. INT Output T11 REFR Output C16 CS Input N10 A[0] Input A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] D[0] / SDO Output / Input T10 D[1] D[2] D[3] D[4] D[5] D[6] D[7] MPM ...
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IDT82P2284 Name Type Pin No. SPIEN Input R11 TRST Input N12 TMS Input R14 TCK Input T14 TDI Input R13 TDO High-Z T13 VDDDIO Power E14 E15 G16 H14 H15 J15 K15 M15 M16 N16 P16 R15 VDDDC Power J10 ...
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IDT82P2284 Name Type Pin No. VDDAT[1] Power B12 VDDAT[2] VDDAT[3] VDDAT[4] VDDAX[1] Power C12 VDDAX[2] VDDAX[3] VDDAX[4] VDDAP Power A13 VDDAB Power D12 GNDA Ground B10 B11 C10 D10 GNDD Ground F13 F15 G10 G13 G15 H10 J14 K13 K14 ...
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IDT82P2284 Name Type Pin No B1, C1, C2, D1, D2, E2, E3, E4, E16, F14, F16, G14, H3, H4, H13, H16, J3, J4, J13, J16, K3, K4, K16, L2, L3, L4, L13, L16, M1, M2, M3, M4, M13, ...
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... The transmit path of each transceiver can be configured to generate SF, ESF SLC- 96. The framer can also be disabled (unframed mode). The Framer can transmit Yellow alarm and AIS alarm. Inband loopback codes and bit oriented message can be transmitted three HDLC links (in ESF ...
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IDT82P2284 TEST AND DIAGNOSES To facilitate the testing and diagnostic functions, Analog Loopback, Remote Digital Loopback, Remote Loopback, Local Digital Loopback, Payload Loopback and System Loopback are also integrated in the IDT82P2284. A programmable pseudo random bit sequence can be ...
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IDT82P2284 3.2 RECEIVER IMPEDANCE MATCHING The receiver impedance matching can be realized by using internal impedance matching circuit or external impedance matching circuit. When the R_TERM[2] bit is ‘0’, the internal impedance matching circuit is enabled. 100 Ω, 110 Ω, ...
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IDT82P2284 In case of LOS, REFH_LOS bit (b0, T1/J1-03EH) determines the outputs on the REFA_OUT and REFB_OUT pins. When set to 0, the output is MCLK; when set to 1, the output is high level. DSX cross connect point R ...
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IDT82P2284 DSX cross connect point DSX cross connect point Table 4: Related Bit / Register In Chapter 3.2 Bit R_TERM[2:0] Transmit And Receive Termination Configuration MG[1:0] Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER RRINGn R RRINGn Figure ...
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IDT82P2284 3.3 ADAPTIVE EQUALIZER The Adaptive Equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation and distortion. Usually, the Adaptive Equalizer is off in short haul applications and long haul ...
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IDT82P2284 the DPLL can be 6. 0.87 Hz, as selected by the RJA_BW bit. The lower the CF is, the longer time is needed to achieve synchroniza- tion. If the incoming data moves faster than the outgoing data, ...
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IDT82P2284 3.7 DECODER 3.7.1 LINE CODE RULE 3.7.1 Mode In T1/J1 mode, the AMI and B8ZS line code rules are provided. The selection is made by the R_MD bit. 3.7.1.2 E1 Mode In E1 mode, the AMI ...
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IDT82P2284 Table 8: Excessive Zero Error Definition ANSI More than 15 consecutive 0s are AMI detected. More than 7 consecutive 0s are B8ZS detected (refer to Figure 9). More than 3 consecutive 0s are HDB3 detected (refer to Figure 10). ...
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IDT82P2284 3.7.3 LOS DETECTION The Loss of Signal (LOS) Detector monitors the amplitude and density of the received signal. When the received signal is below an amplitude for continuous intervals, the LOS is detected. When the received signal is above ...
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IDT82P2284 Table 9: LOS Condition In T1/J1 Mode Loss of Signal in T1/J1 Mode ANSI T1.231 Amplitude below 800 mVpp LOS Detecte Continuous Inter- 175 bits d vals Amplitude above 1 Vpp LOS 12.5% (16 marks in a hopping Cleared ...
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IDT82P2284 Table 11: Related Bit / Register In Chapter 3.7 Bit R_MD EXZ_ERR EXZ_DEF CNT_MD CNT_TRF CNTL[7:0] CNTH[7:0] CV_IS EXZ_IS CNTOV_IS CV_IE EXZ_IE CNT_IE LAC RAISE LOS_S LOS_IES LOS_IS LOS_IE LOS[4:0] Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL ...
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... T1 mode. The Frame Processor acquires frame alignment per ITU-T requirement. When frame alignment is achieved, the Framer Processor continues to monitor the received data stream. The Frame Processor will declare framing bit errors or bit error events if any. The Frame Processor can also detect out-of-frame events based on selected criteria ...
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IDT82P2284 Extended Super Frame (ESF) Format The structure of T1/J1 ESF is illustrated in Table 13. The ESF is made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. The F-bit in Frame ...
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IDT82P2284 T1 Digital Multiplexer (DM) Format (T1 only) The structure illustrated in Table 14. The made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. Except ...
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IDT82P2284 Switch Line Carrier - 96 (SLC-96) Format (T1 only) The structure of SLC-96 is illustrated in Table 15. The SLC-96 is made SFs, but some F-bit are used as Concentrator Bits, Spoiler Bits, Maintenance Bits, Alarm ...
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IDT82P2284 Table 15: The Structure of SLC-96 (Continued) Frame No. F-Bit (Frame Alignment 3.8.1.2 Error Event And Out Of Synchronization Detection After the frame ...
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IDT82P2284 event. This error event is captured by the FERI bit and is for- warded to the Performance Monitor. • DDS Pattern Error: The received 6-bit DDS in each CH24 is com- pared with the DDS pattern - ‘0XX11101’ (MSB ...
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IDT82P2284 Table 16: Interrupt Source In T1/J1 Frame Processor Sources It is out of synchronization. The first bit of each SF / ESF / SLC-96 frame is received. The new-found F bit position differs from the previous ...
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IDT82P2284 Table 17: Related Bit / Register In Chapter 3.8.1 (Continued) Bit RMFBE SFEE BEEE FERE COFAE C[11:1] M[3:1] A[2:1] S[4:1] SCAI SCSI SCMI SCCI SCDEB SCAE SCSE SCME SCCE Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
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... Sa4 to Sa8 can also be extracted and stored in registers, and updated every CRC Sub Multi-Frame. The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0 of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of TS16 of the frame 0 of the Signaling Multi-Frame). The ‘de-bounced’ ...
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IDT82P2284 search for Basic Fframe alignment pattern > 914 CRC search for CRC Multi-Frame errors in alignment pattern if CRCEN = one 1 (refer to CRC Multi-Frame) second Start 8ms and 400ms timer find 2 CRC Multi-Frame alignment patterns within ...
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IDT82P2284 3.8.2.1 Synchronization Searching Basic Frame The algorithm used to search for the E1 Basic Frame alignment pattern (as shown in Figure 12) meets the ITU-T Recommendation G.706 4.1.2 and 4.2. Generally performed by detecting a successive FAS/NFAS/FAS ...
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IDT82P2284 CRC Multi-Frame The CRC Multi-Frame is provided to enhance the ability of verifying the data stream. The structure of TS0 of the CRC Multi-Frame is illus- trated in Table 18. A CRC Multi-Frame consists of 16 continuous Basic Frames ...
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IDT82P2284 CAS Signaling Multi-Frame After the Basic Frame has been synchronized, the Frame Processor starts to search for CAS Signaling Multi-Frame alignment signal if the CASEN bit is ‘1’. The Signaling Multi-Frame alignment pattern is located in the high nibble ...
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IDT82P2284 3.8.2.2 Error Event And Out Of Synchronization Detection After the frame is in synchronization, the Frame Processor keeps on monitoring the received data stream to detect errors and judge out of synchronization. The following ten kinds ...
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IDT82P2284 synchronization again only if the Basic frame is in synchronization. During out of CAS Signaling Multi-Frame synchronization state, the CAS Signaling Multi-Frame Alignment Pattern Error detection is suspended. 3.8.2.3 Overhead Extraction International Bit Extraction The International bits (Si bits, ...
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IDT82P2284 Table 20: Interrupt Source In E1 Frame Processor Sources In CRC to Non-CRC inter-working out of Basic frame synchronization out of CRC multi-frame synchronization out of CAS Signaling multi-frame synchronization. The new-found Basic ...
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IDT82P2284 Table 21: Related Bit / Register In Chapter 3.8.2 Bit UNFM REFEN REFCRCE REFR CRCEN C2NCIWCK CASEN WORDERR CNTNFAS BIT2C SMFASC TS16C OOFV OOCMFV OOOFV C2NCIWV OOSMFV EXCRCERI C2NCIWI OOFI OOCMFI OOSMFI OOOFI OOFE OOCMFE OOOFE C2NCIWE OOSMFE Functional ...
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IDT82P2284 Table 21: Related Bit / Register In Chapter 3.8.2 (Continued) Bit CMFERI FERI CRCEI SMFERI COFAI ICMFPI ICSMFPI ISMFPI CMFERE FERE CRCEE SMFERE COFAE ICMFPE ICSMFPE ISMFPE RAICRCV CFEBEV V52LINKV FEBEI TFEBEI TCRCEI RAICRCI CFEBEI V52LINKI Functional Description QUAD ...
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IDT82P2284 Table 21: Related Bit / Register In Chapter 3.8.2 (Continued) Bit FEBEE TFEBEE TCRCEE RAICRCE CFEBEE V52LINKE Si[0:1] A Sa[4:8] X[0:2] Y SaX[1:4] (‘X’ is from SaXI (‘X’ is from Sa6SCI SaXE (‘X’ ...
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IDT82P2284 3.9 PERFORMANCE MONITOR 3.9.1 T1/J1 MODE Several internal counters are used to count different events for performance monitoring. For different framing format, the counters are used differently. The overflow of each counter is reflected by an Over- flow Indication ...
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IDT82P2284 Table 22: Monitored Events In T1/J1 Mode Format Event Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code Violation (CV) Error (in B8ZS decoding) F Bit Error SF The new-found F bit position differs from the previous one ...
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IDT82P2284 Table 23: Related Bit / Register In Chapter 3.9.1 Bit LCV[15:0] FER[11:0] COFA[2:0] OOF[4:0] PRGD[15:0] CRCE[9:0] DDSE[9:0] LCVOVI FEROVI COFAOVI OOFOVI PRGDOVI CRCOVI DDSOVI LCVOVE FEROVE COFAOVE OOFOVE PRGDOVE CRCOVE DDSOVE LINKSEL[1:0] ADDR[3:0] DAT[7:0] UPDAT AUTOUPD Note ...
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IDT82P2284 3.9.2 E1 MODE Several internal counters are used to count different events for performance monitoring. The overflow of each counter is reflected by an Overflow Indication Bit, and can trigger an interrupt if the corresponding Overflow Interrupt Enable Bit ...
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IDT82P2284 Table 25: Related Bit / Register In Chapter 3.9.2 Bit LCV[15:0] FER[11:0] CRCE[9:0] FEBE[9:0] COFA[2:0] OOF[4:0] PRGD[15:0] TFEBE[9:0] TCRCE[9:0] LCVOVI FEROVI CRCOVI FEBEOVI COFAOVI OOFOVI PRGDOVI TFEBEOVI TCRCOVI LCVOVE FEROVE CRCOVE FEBEOVE COFAOVE OOFOVE PRGDOVE TFEBEOVE TCRCOVE LINKSEL[1:0] ADDR[3:0] ...
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IDT82P2284 3.10 ALARM DETECTOR 3.10.1 T1/J1 MODE The RED alarm, Yellow alarm and Blue alarm are detected in this block (refer to Table 26). Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria Declare Condition The out of SF/ESF/T1 ...
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IDT82P2284 Table 27: Related Bit / Register In Chapter 3.10.1 Bit REDDTH[7:0] REDCTH[7:0] YELDTH[7:0] YELCTH[7:0] AISDTH[7:0] AISCTH[7:0] RED YEL AIS REDI YELI AISI REDE YELE AISE Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Register RED Declare Threshold ...
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IDT82P2284 3.10.2 E1 MODE The Remote alarm, Remote Signaling Multi-Frame alarm, RED alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this block. The Remote Alarm Indication bit is the A bit (refer to Table 18). ...
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IDT82P2284 3.11 HDLC RECEIVER The HDLC Receiver extracts the HDLC data stream from the selected position and processes the data according to the selected mode. 3.11.1 HDLC CHANNEL CONFIGURATION In T1/J1 mode ESF & formats, three HDLC Receivers ...
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IDT82P2284 After the stuffed zero (the zero following five consecutive ’One’s) is discarded, the data stream between the opening flag and the FCS is divided into blocks. Each block (except the last block) has 32 bytes. The block will be ...
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IDT82P2284 Table 30: Interrupt Summarize In HDLC Mode Interrupt Indication Sources Bit A block is pushed into the RMBEI FIFO. Data is still attempted to write OVFLI into the FIFO when the FIFO has been already full (128 bytes). The ...
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IDT82P2284 3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) The Bit-Oriented Message (BOM) can only be received in the ESF format in T1/J1 mode. The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of the F-bit in the ESF format (refer to ...
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... Framer 6 & signaling multi-frame are recognized as ‘A’ and the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the signaling bits A & B will be saved in the Extracted Signaling Data/Extract Enable register, and the C & D bits in the Extracted Signaling Data/ Extract Enable register are Don’ ...
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IDT82P2284 Channel 24 RSDn MRSDA(MRSDB) RSIGn MRSIGA(MRSIGB) 3.15.2 E1 MODE In Signaling Multi-Frame, the signaling bits are located in TS16 (refer to Figure 13), which are Channel Associated ...
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IDT82P2284 Table 35: Related Bit / Register In Chapter 3.15 Bit EXTRACT A,B,C,D DEB FREEZE SIGF (T1/J1 only) SIGE COSI[X] (1 ≤ X ≤ T1/J1) (1 ≤ X ≤ E1) ADDRESS[6:0] RWN D[7:0] BUSY Note: * ...
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IDT82P2284 3.16 RECEIVE PAYLOAD CONTROL Different test patterns can be inserted in the received data stream or the received data stream can be extracted to the PRBS Generator/ Detector for test in this block. To enable all the functions in ...
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IDT82P2284 Table 36: A-Law Digital Milliwatt Pattern Bit 0 Bit 1 Bit 2 Bit 3 Byte Byte Byte Byte Byte ...
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IDT82P2284 Table 38: Related Bit / Register In Chapter 3.16 Bit PCCE SIGFIX (T1/J1 only) POL (T1/J1 only) ABXX (T1/J1 only) TESTEN PRBSDIR PRBSMODE[1:0] TEST STRKEN A,B,C,D GSUBST[2:0] SIGSNAP GSTRKEN DTRK[7:0] SUBST[2:0] SINV OINV EINV ADDRESS[6:0] RWN D[7:0] BUSY Note: ...
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IDT82P2284 3.17 RECEIVE SYSTEM INTERFACE The Receive System Interface determines how to output the received data stream to the system backplane. The data from the four links can be aligned with each other or be output independently. The timing clocks ...
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IDT82P2284 3.17.1.1 Receive Clock Master Mode In the Receive Clock Master mode, each link uses its own timing signal on the RSCKn pin and framing pulse on the RSFSn pin to output the data on each RSDn pin. The signaling ...
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IDT82P2284 1.544 CH3 CH1 CH2 F Mb/s 2.048 TS0 TS1 TS2 TS3 Mb/s filler the 8th bit Figure 19. T1/ Format Mapping - One Filler Every Fourth Channel Mode 1.544 CH1 CH2 F Mb/s 2.048 TS0 TS1 TS2 ...
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IDT82P2284 arranged by setting the channel offset. The data from different links on one multiplexed bus must be shifted at a different channel offset to avoid data mixing. In the Receive Multiplexed mode, the timing signal on the MRSCK pin ...
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IDT82P2284 Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Figure 22. No Offset When & ...
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IDT82P2284 Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Figure 24. No Offset When & ...
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IDT82P2284 3.17.2 E1 MODE In E1 mode, the Receive System Interface can be set in Non-multi- plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the RSDn pin is used to output the received data from each link at the ...
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IDT82P2284 In the Receive Clock Slave mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn used to sample the pulse on the RSFSn is determined by the FE bit. The active ...
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IDT82P2284 Table 41: Related Bit / Register In Chapter 3.17 Bit RMUX RSLVCK RMODE MAP[1:0] (T1/J1 only) G56K GAP FBITGAP (T1/J1 only CMS TRI PCCE CMFS ALTIFS (T1/J1 only) FSINV OHD (E1 only) SMFS (E1 only) EDGE BOFF[2:0] ...
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IDT82P2284 3.18 TRANSMIT SYSTEM INTERFACE The Transmit System Interface determines how to input the data to the device. The data input to the four links can be aligned with each other or input independently. The timing clocks and framing pulses ...
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IDT82P2284 3.18.1.1 Transmit Clock Master Mode In the Transmit Clock Master mode, each link uses its own timing signal on the TSCKn pin and framing pulse on the TSFSn pin to input the data on each TSDn pin. The signaling ...
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IDT82P2284 discarded the 8th bit 2.048 TS0 TS1 TS2 TS3 Mb/s 1.544 CH1 CH2 CH3 F Mb/s Figure 26 T1/J1 Format Mapping - One Filler Every Fourth Channel Mode the 8th bit discarded 2.048 TS0 TS1 TS2 Mb/s ...
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IDT82P2284 arranged by setting the channel offset. The data to different links from one multiplexed bus must be shifted at a different channel offset to avoid data mixing. In the Transmit Multiplexed mode, the timing signal on the MTSCK pin ...
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IDT82P2284 Transmit Clock Slave mode / Transmit Multiplexed mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Transmit Clock Master mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Figure 29. No Offset When & ...
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IDT82P2284 Transmit Clock Slave mode / Transmit Multiplexed mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Transmit Clock Master mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Figure 31. No Offset When & ...
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IDT82P2284 3.18.2 E1 MODE In E1 mode, the Transmit System Interface can be set in Non-multi- plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the TSDn pin is used to input the data to each link at the bit ...
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IDT82P2284 3.18.2.1 Transmit Clock Master Mode In the Transmit Clock Master mode, each link uses its own timing signal on the TSCKn pin and framing pulse on the TSFSn pin to input the data on each TSDn pin. The signaling ...
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IDT82P2284 MTSDA(MTSDB) pin. The signaling MTSIGA(MTSIGB) pin are always per-timeslot aligned with the data on the TSDn/MTSDA(MTSDB) pin. Refer to Chapter 3.18.1.4 Offset for the base line without offset in different operating modes and the configuration of the offset. In ...
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IDT82P2284 The following methods can be executed on the signaling bits input from the TSIGn/MTSIGA (MTSIGB) pins on a per-channel/per-TS basis global basis of the corresponding link. The processed signaling bits will be inserted to the data ...
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IDT82P2284 3.20 FRAME GENERATOR 3.20.1 GENERATION 3.20.1 Mode In T1/J1 mode, the data to be transmitted can be generated as Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) format. ...
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IDT82P2284 When the FDIS bit and the FDLBYP bit are both ‘0’s, the contents in the XDL0, XDL1 & XDL2 registers will replace the Concentrator (C) bits, the Maintenance (M) bits, the Alarm (A) bits and the Switch (S) bits ...
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IDT82P2284 3.20.1.2 E1 Mode In E1 mode, the Frame Generator can generate Basic Frame, CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi-Frame. The Frame Generator can also transmit alarm indication signal when special conditions occurs in the received data stream. ...
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IDT82P2284 When the Modified CRC Multi-Frame is generated, only the Sa bit position and the calculated CRC-4 bit position can be changed. All the other bits are transparently transmitted unless all ’One’s or all ‘Zero’s are transmitted (refer to Chapter ...
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IDT82P2284 Table 50: Related Bit / Register In Chapter 3.20.1.2 Bit REMAIS AUTOYELLOW G706RAI MFAIS TS16LOS TS16AIS SaX[1:4] (‘X’ is from SaXEN (‘X’ is from OOCMFV X[0:2] FASI BFI MFI SMFI SIGMFI FASE BFE ...
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IDT82P2284 3.20.2 HDLC TRANSMITTER The HDLC Transmitter inserts the data into the selected position to form HDLC packet data stream. 3.20.2.1 HDLC Channel Configuration In T1/J1 mode ESF & formats, three HDLC Transmitters (#1, #2 & #3) per ...
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IDT82P2284 Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 Bit THDLCM EOM THDLC1 Control / THDLC2 Control / THDLC3 Control ABORT TRST DAT[7:0] THDLC1 Data / THDLC2 Data / THDLC3 Data FUL EMP TFIFO1 Status / ...
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IDT82P2284 3.20.3 AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/J1 ONLY) The Automatic Performance Report Message (APRM) can only be transmitted in the ESF format in T1/J1 mode. Five kinds of events are counted every second in the APRM: • The Bipolar Violation ...
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IDT82P2284 Table 54: APRM Interpretation A Logic 1 In The Following Bit Position Table 55: Related Bit / Register In Chapter 3.20.3 Bit Register AUTOPRM CRBIT RBIT APRM Control U1BIT ...
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IDT82P2284 3.20.6 ALL ‘ZERO’S & ALL ‘ONE’S After all the above processes, all ’One’s or all ‘Zero’s will overwrite all the data stream if the TAIS bit and the TXDIS bit are set. The all zeros transmission takes a higher ...
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IDT82P2284 3.22 ENCODER 3.22.1 LINE CODE RULE 3.22.1.1 T1/J1 Mode In T1/J1 mode, the B8ZS line code rule or the AMI line code rule can be selected by the T_MD bit. 3.22.1.2 E1 Mode In E1 mode, the HDB3 line ...
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IDT82P2284 Table 59: Related Bit / Register In Chapter 3.23 Bit Register TJA_E TJA_DP[1:0] Transmit Jitter Attenuation Configura- TJA_BW tion TJA_LIMT TJITT_TEST TJA_IS Interrupt Status 1 TJA_IE Interrupt Enable Control 1 Transmit Jitter Measure Value Indica- TJITT[6:0] tion Functional Description ...
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IDT82P2284 Table 60: PULS[3:0] Setting In T1/J1 Mode Cable Configuration 133 133 ~ 266 266 ~ 399 399 ~ 533 533 ~ 655 ft ...
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IDT82P2284 or down at the percentage ratio against the standard pulse amplitude if necessary. For different pulse shapes, the value of the SCAL[5:0] bits and the scaling percentage ratio are different. The values are listed in Table 62 to Table ...
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IDT82P2284 Table 63: Transmit Waveform Value For E1 120 Ω Sample 1 0000000 0000000 Sample 2 0000000 0000000 Sample 3 0000000 0000000 Sample 4 0001111 0000000 Sample 5 0111100 0000000 Sample 6 0111100 0000000 Sample 7 ...
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IDT82P2284 Table 65: Transmit Waveform Value For T1 133~266 Sample 1 0011011 1000011 Sample 2 0101100 1000010 Sample 3 0101011 1000001 Sample 4 0101010 0000000 Sample 5 0101000 0000000 Sample 6 0101000 0000000 Sample 7 ...
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IDT82P2284 Table 67: Transmit Waveform Value For T1 399~533 Sample 1 0100000 1000011 Sample 2 0111000 1000010 Sample 3 0110011 1000001 Sample 4 0101111 0000000 Sample 5 0101110 0000000 Sample 6 0101101 0000000 Sample 7 ...
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IDT82P2284 Table 69: Transmit Waveform Value For J1 0~655ft Sample 1 0010111 1000010 Sample 2 0100111 1000001 Sample 3 0100111 0000000 Sample 4 0100110 0000000 Sample 5 0100101 0000000 Sample 6 0100101 0000000 Sample 7 0100101 ...
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IDT82P2284 Table 71: Transmit Waveform Value For DS1 -7.5 dB LBO Sample 1 0000000 0010100 Sample 2 0000010 0010010 Sample 3 0001001 0010000 Sample 4 0010011 0001110 Sample 5 0011101 0001100 Sample 6 0100101 0001011 Sample ...
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IDT82P2284 Table 73: Transmit Waveform Value For DS1 -22.5 dB LBO Sample 1 0000000 0101100 Sample 2 0000000 0101110 Sample 3 0000000 0110000 Sample 4 0000000 0110001 Sample 5 0000001 0110010 Sample 6 0000011 0110010 Sample ...
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IDT82P2284 3.25 LINE DRIVER The Line Driver can be set to High-Z for redundant application. The following ways will set the drivers to High-Z: - Setting the THZ pin to high will globally set all the Line Drivers to High-Z; ...
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IDT82P2284 The selected pattern is generated once there is a transition from ‘0’ to ‘1’ on the TESTEN bit. A single bit error will be inserted to the generated pattern when the INV bit is set to ‘1’. Before the ...
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IDT82P2284 3.27.2 LOOPBACK System Loopback, Payload Loopback, Local Digital Loopback 1 & 2, Remote Loopback and Analog Loopback are all supported in the IDT82P2284. Their routes are shown in the Functional Block Diagram. 3.27.2.1 System Loopback The System Loopback can ...
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IDT82P2284 The G.772 Non-Intrusive Monitoring meets the ITU-T G.772 shown in Figure 36. The data stream of Link 1 is received from the selected path of any of the remaining links, then processed as normal. The operation of ...
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IDT82P2284 Table 78: Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 Bit SRLP SLLP DLLP RLP DLP ALP GSUBST[2:0] SUBST[2:0] MON[3:0] Note means Indirect Register in the Transmit Payload Control function block. 3.28 INTERRUPT SUMMARY When ...
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IDT82P2284 Table 79: Related Bit / Register In Chapter 3.28 Bit TMOVI INT[4:1] TMOVE LIU IBCD (T1/J1 only) RBOC (T1/J1 only) ALARM PMON PRGD RCRB FGEN FRMR THDLC3 THDLC2 THDLC1 RHDLC3 RHDLC2 RHDLC1 ELST TRSI/RESI Functional Description QUAD T1/E1/J1 LONG ...
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IDT82P2284 4 OPERATION 4.1 POWER-ON SEQUENCE To power on the device, the following sequence should be followed: • Apply ground; • Apply 3.3 V; • Apply 1.8 V. 4.2 RESET When the device is powered-up, all the registers contain random ...
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IDT82P2284 4.4.1 SPI MODE Pull the SPIEN pin to high, and the microprocessor interface will be set in SPI mode. In this mode, only the CS, SCLK, SDI and SDO pins are interfaced with the microprocessor. A falling transition on ...
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IDT82P2284 4.5 INDIRECT REGISTER ACCESS SCHEME In Receive CAS/RBS Buffer, Receive Payload Control and Transmit Payload Control blocks, per-channel/per-timeslot indirect register is accessed by using an indirect register access scheme. 4.5.1 INDIRECT REGISTER READ ACCESS The indirect register read access ...
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IDT82P2284 5 PROGRAMMING INFORMATION 5.1 REGISTER MAP In the ‘Reg’ column, the ‘X’ represents corresponding to the four links. 5.1.1 T1/J1 MODE 5.1.1.1 Direct Register T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) 001 ID7 ID6 ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X2B - DLLP SLLP X2C - - X2D ~ - - X30 X31 - BPV_INS X32 - - T_TERM2 T_TERM1 T_TERM0 X33 - - X34 - DAC_IE TJA_IE X35 - ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X4B - - X4C - - X4D - - X4E - - X4F - - X50 - - X51 - - X52 - - EXCRCE RI X53 - - X54 ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X74 - - X75 IBC7 IBC6 IBC5 X76 - - X77 - - X78 ACT7 ACT6 ACT5 X79 DACT7 DACT6 DACT5 X7A - - X7B - - X7C - - ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X95 - - X96 - - X97 - - X98 DAT7 DAT6 DAT5 X99 DAT7 DAT6 DAT5 X9A DAT7 DAT6 DAT5 X9B - - X9C - - X9D - - ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) XB7 - - XB8 - - XB9 - - XBA - - XBB - - XBC REDDTH7 REDDTH6 REDDTH5 REDDTH4 REDDTH3 REDDTH2 REDDTH1 REDDTH0 RED Declare Threshold XBD REDCTH7 REDCTH6 ...
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IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) XD6 COSI8 COSI7 COSI6 XD7 COSI16 COSI15 COSI14 XD8 COSI24 COSI23 COSI22 Note: * The Reference Clock Output Control register (addressed X3E) is available in ZB revision only, otherwise, it ...
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IDT82P2284 5.1.1.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 08 LCV7 ...
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IDT82P2284 5.1.2 E1 MODE 5.1.2.1 Direct Register E1 Reg Bit 7 Bit 6 Bit 5 (Hex) 001 ID7 ID6 ID5 002 ~ - - - 003 004 - - - 005 - - - 006 - - - 007 - ...
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IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X2D ~ - - - X30 X31 - BPV_INS - X32 - - T_TERM2 X33 - - - X34 - DAC_IE TJA_IE X35 - - - X36 - - - ...
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IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X4F - - - X50 - - - X51 ISMFPE ICSMFPE SMFERE X52 - - EXCRCER I X53 ISMFPI ICSMFPI SMFERI X54 Si0 Si1 A X55 - - - X56 ...
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IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X70 - - - X71 - - - X72 - - - X73 - - - X74 ~ - - - X7B X7C - - - X7D - - - ...
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IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X9A DAT7 DAT6 DAT5 X9B - - - X9C - - - X9D - - - X9E - - - X9F - - - XA0 - - - XA1 HA7 ...
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IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) XBC - - - XBD ~ - - - XC1 XC2 - - - XC3 PRDGOV TFE- FEBEOVE TCRCOVE COFAOVE E BEOVE XC4 - - - XC5 PRDGOVI TFE- FEBEOVI ...
Page 133
IDT82P2284 5.1.2.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 PRGD12 08 ...
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IDT82P2284 TPLC Address (Hex) Bit 7 Bit 6 Bit SUBST2 SUBST SUBST0 DTRK7 DTRK6 DTRK5 TEST TEST Programming Information QUAD T1/E1/J1 LONG HAUL / ...
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IDT82P2284 5.2 REGISTER DESCRIPTION Depending on the operating mode, the registers are configured for T1/J1 or E1. Before setting any other registers, the operating mode should be selected in registers 020H, 120H, 220H and 320H. According to the access method, ...
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IDT82P2284 5.2.1 T1/J1 MODE 5.2.1.1 Direct Register T1/J1 Chip ID For Quad Transceiver (001H) Bit No. 7 Bit Name ID7 Type R Default 0 ID[7:0]: The ID[7:0] bits are pre-set. The ID[7:4] bits represent the IDT82P2284 device. The ID[3:0] bits ...
Page 137
IDT82P2284 T1/J1 G.772 Monitor Control (005H) Bit No Bit Name Type Default MON[3:0]: These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one transmitter or receiver to be monitored ...
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IDT82P2284 T1/J1 GPIO Control (006H) Bit No. 7 Bit Name Type Default LEVEL[1]: When the GPIO[1] pin is defined as an output port, this bit can be read and written The GPIO[1] pin outputs low level ...
Page 139
IDT82P2284 T1/J1 Reference Clock Output Select (007H) Bit No Bit Name Type Reserved Default RO2[1:0]: When no LOS is detected, the REFB_OUT pin outputs a recovered clock from the Clock and Data Recovery function block of one of ...
Page 140
IDT82P2284 T1/J1 Interrupt Requisition Link ID (009H) Bit No. 7 Bit Name Type Default INTn interrupt is generated in the corresponding link least one interrupt is generated in the corresponding link. T1/J1 Timer Interrupt ...
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IDT82P2284 T1/J1 PMON Access Port (00EH) Bit No. 7 Bit Name LINKSEL1 Type Reserved R/W Default LINKSEL[1:0]: These bits select one of the four links. One of the PMON indirect registers of the selected link can be accessed by the ...
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IDT82P2284 T1/J1 Backplane Global Configuration (010H) Bit No. 7 Bit Name Type Reserved Default RSLVCK: This bit is valid when all four links are in the Receive Clock Slave mode Each link uses its own clock signal on ...
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IDT82P2284 T1/J1 Transmit Jitter Attenuation Configuration (021H, 121H, 221H, 321H) Bit No. 7 Bit Name Type Reserved Default TJITT_TEST The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits ...
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IDT82P2284 T1/J1 Transmit Configuration 0 (022H, 122H, 222H, 322H) Bit No. 7 Bit Name Type Reserved Default T_OFF The transmit path is power up The transmit path is power down. The Line Driver is in high ...
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IDT82P2284 T1/J1 Transmit Configuration 1 (023H, 123H, 223H, 323H) Bit No. 7 Bit Name Type Reserved Default DFM_ON The Driver Failure Monitor is disabled The Driver Failure Monitor is enabled. T_HZ The Line Driver ...
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IDT82P2284 T1/J1 Transmit Configuration 2 (024H, 124H, 224H, 324H) Bit No. 7 Bit Name Type Reserved Default SCAL[5:0]: The following setting lists the standard values of normal amplitude in different operating modes. Each step change (one increasing or decreasing from ...
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IDT82P2284 T1/J1 Transmit Configuration 3 (025H, 125H, 225H, 325H) Bit No Bit Name DONE RW Type R/W R/W Default 0 0 This register is valid when the PULS[3:0] bits (b3~0, T1/J1-023H,...) are set to ‘11xx’. DONE ...
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IDT82P2284 T1/J1 Transmit Configuration 4 (026H, 126H, 226H, 326H) Bit No Bit Name WDAT6 Type Reserved R/W Default 0 WDAT[6:0]: These bits contain the data to be stored in the pulse template RAM which is addressed by the ...
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IDT82P2284 T1/J1 Receive Configuration 0 (028H, 128H, 228H, 328H) Bit No. 7 Bit Name Type Reserved Default R_OFF The receive path is power up The receive path is power down. R_MD: This bit selects the line ...
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IDT82P2284 T1/J1 Receive Configuration 1 (029H, 129H, 229H, 329H) Bit No Bit Name EQ_ON Type Reserved R/W Default 0 EQ_ON The Equalizer is off in short haul applications The Equalizer long ...
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IDT82P2284 T1/J1 Receive Configuration 2 (02AH, 12AH, 22AH, 32AH) Bit No Bit Name Type Reserved Default SLICE[1:0]: These two bits define the Data Slicer threshold. = 00: The Data Slicer generates a mark if the voltage on the ...
Page 152
IDT82P2284 T1/J1 Maintenance Function Control 0 (02BH, 12BH, 22BH, 32BH) Bit No Bit Name DLLP Type Reserved R/W Default 0 DLLP Disable the Local Digital Loopback Enable the Local Digital Loopback 1. SLLP: ...
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IDT82P2284 T1/J1 Maintenance Function Control 1 (02CH, 12CH, 22CH, 32CH) Bit No Bit Name Type Default LAC: This bit selects the LOS criterion The T1.231 is selected. In short haul application, the LOS is declared when ...
Page 154
IDT82P2284 T1/J1 Maintenance Function Control 2 (031H, 131H, 231H, 331H) Bit No Bit Name BPV_INS Type Reserved R/W Default 0 BPV_INS: A transition from ‘0’ to ‘1’ on this bit generates a single Bipolar Violation (BPV) Error to ...
Page 155
IDT82P2284 T1/J1 Transmit And Receive Termination Configuration (032H, 132H, 232H, 332H) Bit No Bit Name Type Reserved Default T_TERM[2:0]: These bits select the internal impedance of the transmit path to match the cable impedance: = 000: The 75 ...
Page 156
IDT82P2284 T1/J1 Interrupt Enable Control 1 (034H, 134H, 234H, 334H) Bit No Bit Name DAC_IE Type Reserved R/W Default 0 DAC_IE Disable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’. ...
Page 157
IDT82P2284 T1/J1 Line Status Register 0 (036H, 136H, 236H, 336H) Bit No Bit Name Type Default DF_S transmit driver failure is detected Transmit driver failure is detected. LOS_S LOS is ...
Page 158
IDT82P2284 T1/J1 Transmit Jitter Measure Value Indication (038H, 138H, 238H, 338H) Bit No Bit Name TJITT6 Type Reserved R Default 0 TJITT[6:0]: When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘0’, these bits represent the current interval between the ...
Page 159
IDT82P2284 T1/J1 Interrupt Status 0 (03AH, 13AH, 23AH, 33AH) Bit No Bit Name Type Default DF_IS There is no status change on the DF_S bit (b2, T1/J1-036H,...). = 1: When the DF_IES bit (b2, T1/J1-035H,...) is ...
Page 160
IDT82P2284 T1/J1 Interrupt Status 1 (03BH, 13BH, 23BH, 33BH) Bit No Bit Name DAC_IS Type Reserved R Default 0 DAC_IS The sum of a pulse template does not exceed the D/A limitation (+63) when more than ...
Page 161
IDT82P2284 T1/J1 EXZ Error Counter H-Byte (03CH, 13CH, 23CH, 33CH) Bit No Bit Name CNTH[7] CNTH[6] Type R R Default 0 0 CNTH[7:0]: These bits, together with the CNTL[7:0] bits, reflect the content in the internal 16-bit EXZ ...
Page 162
IDT82P2284 T1/J1 Reference Clock Output Control (03EH, 13EH, 23EH, 33EH) Bit No Bit Name Type Default REFH_LOS: In case of LOS, this bit determines the outputs on the REFA_OUT and REFB_OUT pins Output MCLK ...
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IDT82P2284 T1/J1 Interrupt Module Indication 0 (040H, 140H, 240H, 340H) Bit No Bit Name IBCD RBOC Type R R Default 0 0 IBCD interrupt is generated in the Inband Loopback Code Detector function block. = ...
Page 164
IDT82P2284 T1/J1 Interrupt Module Indication 1 (041H, 141H, 241H, 341H) Bit No Bit Name THDLC3 THDLC2 Type R R Default 0 0 THDLC3 interrupt is generated in the HDLC Transmitter #3 function block ...
Page 165
IDT82P2284 T1/J1 TBIF Option Register (042H, 142H, 242H, 342H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Transmit Clock Master mode The F-bit is not gapped The F-bit is ...
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IDT82P2284 T1/J1 TBIF Operating Mode (043H, 143H, 243H, 343H) Bit No Bit Name Type Default MAP[1:0]: In Transmit Clock Slave mode and Transmit Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: ...
Page 167
IDT82P2284 T1/J1 TBIF Bit Offset (045H, 145H, 245H, 345H) Bit No Bit Name Type Default EDGE: This bit is valid when the CMS bit (b2, T1/J1-042H,...) is ‘1’ The first active edge of TSCKn/MTSCK is selected ...
Page 168
IDT82P2284 T1/J1 RBIF Option Register (046H, 146H, 246H, 346H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Receive Clock Master mode The F-bit is not gapped The F-bit is ...
Page 169
IDT82P2284 T1/J1 RBIF Mode (047H, 147H, 247H, 347H) Bit No Bit Name Type Default MAP[1:0]: In Receive Clock Slave mode and Receive Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: * ...
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IDT82P2284 T1/J1 RBIF Frame Pulse (048H, 148H, 248H, 348H) Bit No Bit Name Type Reserved Default FSINV The receive framing pulse RSFSn is active high The receive framing pulse RSFSn is active low. In ...
Page 171
IDT82P2284 T1/J1 RBIF TS Offset (049H, 149H, 249H, 349H) Bit No Bit Name TSOFF6 Type Reserved R/W Default 0 TSOFF[6:0]: These bits give a binary number to define the channel offset. The channel offset is between the framing ...
Page 172
IDT82P2284 T1/J1 RTSFS Change Indication (04BH, 14BH, 24BH, 34BH) Bit No Bit Name Type Default RCOFAI: This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode The interval of the pulses on the ...
Page 173
IDT82P2284 T1/J1 FRMR Mode 0 (04DH, 14DH, 24DH, 34DH) Bit No Bit Name Type Default UNFM The data stream is received in framed mode and is processed by the Frame Processor The data stream ...
Page 174
IDT82P2284 T1/J1 FRMR Mode 1 (04EH, 14EH, 24EH, 34EH) Bit No Bit Name Type Default DDSC: This bit selects the synchronization criteria format correct DDS pattern is received before the first ...
Page 175
IDT82P2284 T1/J1 FRMR Status (04FH, 14FH, 24FH, 34FH) Bit No Bit Name Type Default OOFV The SF/ESF/T1 DM/SLC-96 frame is in synchronization The frame is out of synchronization. T1/J1 FRMR Interrupt Control 0 (050H, ...
Page 176
IDT82P2284 T1/J1 FRMR Interrupt Control 1 (051H, 151H, 251H, 351H) Bit No Bit Name Type Reserved Default RMFBE Disable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’ Enable ...
Page 177
IDT82P2284 T1/J1 FRMR Interrupt Indication 0 (052H, 152H, 252H, 352H) Bit No Bit Name Type Reserved Default EXCRCERI: In ESF format, once the accumulated CRC-6 errors exceed 319 (>319 second fixed window, an excessive CRC-6 ...
Page 178
IDT82P2284 T1/J1 FRMR Interrupt Indication 1 (053H, 153H, 253H, 353H) Bit No Bit Name Type Reserved Default RMFBI The received bit is not the first bit of each SF/ESF/T1 DM/SLC-96 frame The first bit ...
Page 179
IDT82P2284 In SLC-96 format, The Ft bit in each odd frame and the Fs bit in Frame (2n) (0<n<12 and n=36) is compared with the expected one (refer to Table 15). Each unmatched bit leads to a F-bit error event. ...
Page 180
IDT82P2284 T1/J1 RDL2 (058H, 158H, 258H, 358H) Bit No Bit Name Type Reserved Default S[4:1]: In SLC-96 format, these bits reflect the content in the Switch bits. The S[1] bit is the LSB. In de-bounce condition, these bits ...
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IDT82P2284 T1/J1 DLB Interrupt Control (05CH, 15CH, 25CH, 35CH) Bit No Bit Name Type Reserved Default SCDEB Disable the de-bounce function of the overhead extraction Enable the de-dounce function of the overhead extraction. SCAE: ...
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IDT82P2284 T1/J1 Mode (062H, 162H, 262H, 362H) Bit No Bit Name Type Default FDLBYP: In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Enable the DL bit position to be ...
Page 183
IDT82P2284 T1/J1 XDL1 (066H, 166H, 266H, 366H) Bit No Bit Name Type Reserved Default M[3:1]: These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They ...
Page 184
IDT82P2284 T1/J1 FGEN Maintenance 1 (06CH, 16CH, 26CH, 36CH) Bit No Bit Name Type Default MIMICEN: This bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Disable the mimic pattern insertion The ...
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IDT82P2284 T1/J1 FGEN Interrupt Indication (06EH, 16EH, 26EH, 36EH) Bit No Bit Name Type Default MFI The bit input to the Frame Generator is not the first bit of each SF/ESF/T1 DM/SLC-96 multiframe The ...
Page 186
IDT82P2284 T1/J1 Error Insertion (06FH, 16FH, 26FH, 36FH) Bit No Bit Name Type Default DDSINV: This bit is valid format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’. A transition from ‘0’ to ‘1’ on ...
Page 187
IDT82P2284 T1/J1 Transmit Timing Option (070H, 170H, 270H, 370H) Bit No Bit Name Type Default XTS: In Transmit Clock Master mode The source of the transmit clock is selected from the clock generated by the internal ...
Page 188
IDT82P2284 T1/J1 PRGD Status/Error Control (072H, 172H, 272H, 372H) Bit No Bit Name Type Default BERE Disable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’ Enable the interrupt ...
Page 189
IDT82P2284 T1/J1 XIBC Control (074H, 174H, 274H, 374H) Bit No Bit Name Type Default IBCDEN Disable transmitting the inband loopback code Enable transmitting the inband loopback code. IBCDUNFM The inband loopback code ...
Page 190
IDT82P2284 T1/J1 IBCD Detector Configuration (076H, 176H, 276H, 376H) Bit No Bit Name Type Reserved Default IBCDIDLE The F-bit is compared with the target activate/deactivate inband loopback code, but the result of the F-bit comparison is ...
Page 191
IDT82P2284 T1/J1 IBCD Detector Status (077H, 177H, 277H, 377H) Bit No Bit Name Type Default LBA The activate code is loss. That is, more than 600 bits are not matched with the target activate inband loopback ...
Page 192
IDT82P2284 T1/J1 IBCD Interrupt Control (07AH, 17AH, 27AH, 37AH) Bit No Bit Name Type Default LBAE Disable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’ Enable the interrupt ...
Page 193
IDT82P2284 T1/J1 ELST Configuration (07CH, 17CH, 27CH, 37CH) Bit No Bit Name Type Default TRKEN: In Receive Clock Slave mode and Receive Multiplexed mode out of synchronization, the trunk code programmed in the TRKCODE[7:0] bits ...
Page 194
IDT82P2284 T1/J1 APRM Control (07FH, 17FH, 27FH, 37FH) Bit No Bit Name Type Reserved Default LBBIT: This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be ...
Page 195
IDT82P2284 T1/J1 BOC Control (081H, 181H, 281H, 381H) Bit No Bit Name Type Default AVC: This bit selects the validation criteria used to declare the Bit Oriented Message (BOM) in the received data stream only valid ...
Page 196
IDT82P2284 T1/J1 THDLC Enable Control (084H, 184H, 284H, 384H) Bit No Bit Name Type Default TDLEN3 All the functions of the HDLC Transmitter #3 is disabled All the functions of the HDLC Transmitter #3 ...
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IDT82P2284 T1/J1 THDLC3 Assignment (087H, 187H, 287H, 387H) Bit No Bit Name EVEN Type Reserved R/W Default 0 The function of the above two sets of registers are the same. However, they correspond to different THDLC. EVEN: = ...
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IDT82P2284 T1/J1 THDLC2 Bit Select (089H, 189H, 289H, 389H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 T1/J1 THDLC3 Bit Select (08AH, 18AH, 28AH, 38AH) Bit No Bit Name BITEN7 BITEN6 Type ...
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IDT82P2284 T1/J1 RHDLC2 Assignment (08DH, 18DH, 28DH, 38DH) Bit No Bit Name EVEN Type Reserved R/W Default 0 T1/J1 RHDLC3 Assignment (08EH, 18EH, 28EH, 38EH) Bit No Bit Name EVEN Type Reserved R/W Default 0 The ...
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IDT82P2284 T1/J1 RHDLC3 Bit Select (091H, 191H, 291H, 391H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 The function of the above two sets of registers are the same. However, they correspond to different ...