82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 119

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

5
5.1
5.1.1
5.1.1.1 Direct Register
Programming Information
IDT82P2284
T1/J1 Reg
002 ~ 003
011 ~ 01F
In the ‘Reg’ column, the ‘X’ represents 0 ~ 3, corresponding to the four links.
00C ~
(Hex)
X2A
00A
00B
00D
00E
00F
X20
X21
X22
X23
X24
X25
X26
X27
X28
X29
001
004
005
006
007
008
009
010
PROGRAMMING INFORMATION
REGISTER MAP
T1/J1 MODE
DONE
DAT7
Bit 7
ID7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LINKSEL1 LINKSEL0
WDAT6
EQ_ON
DAT6
Bit 6
ID6
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RJITT_TE
TJITT_TE
DFM_ON
WDAT5
SLICE1
SCAL5
DAT5
Bit 5
ID5
UI1
ST
ST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RJA_LIMT
TJA_LIMT
RSLVCK
WDAT4
SLICE0
R_OFF
T_OFF
SCAL4
RO21
DAT4
T_HZ
LOS4
Bit 4
ID4
UI0
-
-
-
-
-
-
-
-
-
-
-
-
LEVEL1
UPDW1
WDAT3
ADDR3
SAMP3
PULS3
SCAL3
RJA_E
RMUX
TJA_E
MON3
RO20
DAT3
T1/J1
LOS3
Bit 3
INT4
ID3
-
-
-
-
-
-
-
-
-
TJA_DP1
RJA_DP1
119
LEVEL0
UPDW0
MTSDA
ADDR2
SAMP2
WDAT2
PULS2
SCAL2
MON2
LOS2
DAT2
Bit 2
INT3
FM1
ID2
-
-
-
-
-
-
-
-
-
-
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RJA_DP0
TJA_DP0
TSLVCK
ADDR1
WDAT1
SAMP1
PULS1
SCAL1
MON1
RO11
DAT1
LOS1
DIR1
Bit 1
INT2
MG1
FM0
ID1
-
-
-
-
-
-
-
-
-
TEMODE
RJA_BW
TJA_BW
TMOVE
WDAT0
ADDR0
SAMP0
TMOVI
PULS0
SCAL0
MON0
TMUX
R_MD
RO10
T_MD
DAT0
LOS0
Bit 0
DIR0
INT1
MG0
ID0
-
-
-
-
-
Chip ID For Quad Transceiver
Reserved
Software Reset
G.772 Monitor Control
GPIO Control
Reference
Select
Reserved
Interrupt Requisition Link ID
Timer Interrupt Control
Timer Interrupt Indication
Reserved
PMON Access Port
PMON Access Data
Backplane Global Configura-
tion
Reserved
T1/J1 Or E1 Mode
Transmit Jitter Attenuation
Configuration
Transmit Configuration 0
Transmit Configuration 1
Transmit Configuration 2
Transmit Configuration 3
Transmit Configuration 4
Receive Jitter Attenuation
Configuration
Receive Configuration 0
Receive Configuration 1
Receive Configuration 2
Register Name
Clock
February 25, 2008
Output
Reference
P 136
P 136
P 137
P 138
P 139
P 140
P 140
P 140
P 141
P 141
P 142
P 135
P 143
P 144
P 145
P 146
P 148
P 148
P 149
P 150
P 151
P 147
Page
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