82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 116

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

4
4.1
4.2
values.
power-up and the low signal should last at least 10 ms to initialize the
device. After the RESET pin is asserted high, all the registers are in their
default values and can be accessed after 2 ms (refer to Figure 37).
software anytime. When it is hardware reset, the RESET pin should be
asserted low for at least 100 ns. Then all the registers are in their default
values and can be accessed after 2 ms (refer to Figure 38). When it is
software reset, a write signal to the Software Reset register will reset all
the registers except the T1/J1 Or E1 Mode register to their default
values. Then the registers are accessible after 2 ms. However, the T1/J1
Or E1 Mode register can not be reset by the software reset. It can only
be reset by the hardware reset.
Mode register is changed, a software reset must be applied.
Operation
IDT82P2284
To power on the device, the following sequence should be followed:
• Apply ground;
• Apply 3.3 V;
• Apply 1.8 V.
When the device is powered-up, all the registers contain random
The hardware reset pin RESET must be asserted low during the
During normal operation, the device can be reset by hardware or
It should be mentioned that when the setting in the T1/J1 Or E1
OPERATION
POWER-ON SEQUENCE
RESET
116
4.3
setting the R_OFF bit. During the receive path power down, the output
of the corresponding path is low.
by the T_OFF bit. During the transmit path power down, the output of the
corresponding path is High-Z.
4.4
registers in the device. The interface consists of Serial Peripheral Inter-
face (SPI) and parallel microprocessor interface.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The receive path of any of the four links can be power down by
The transmit path of any of the four links can be set to power down
The microprocessor interface provides access to read and write the
Microprocessor
Microprocessor
Figure 38. Hardware Reset In Normal Operation
Figure 37. Hardware Reset When Powered-Up
Interface
Interface
RESET
RESET
RECEIVE / TRANSMIT PATH POWER DOWN
MICROPROCESSOR INTERFACE
Vdd
10ms
100 ns
2ms
2ms
February 25, 2008
access
access