82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 15

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Pin Description
IDT82P2284
TSD[1] / MTSDA[1]
TSD[2] / MTSDB[1]
RSCK[1] / MRSCK
RSFS[1] / MRSFS
RSCK[2]
RSCK[3]
RSCK[4]
RSFS[2]
RSFS[3]
RSFS[4]
TSD[3]
TSD[4]
Name
Output / Input
Output / Input
Type
Input
Pin No.
N5
R4
N4
R3
G2
G3
P5
T4
P4
T3
F2
F3
RSFS[1:4]: Receive Side System Frame Pulse for Link 1 ~ 4
In T1/J1 Receive Clock Master mode, RSFSn outputs the pulse to indicate each F-bit, every second F-bit in
SF frame, the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame or the first F-bit of every second SF
multi-frame.
In T1/J1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate
the start of a frame.
In E1 Receive Clock Master mode, RSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame,
Signaling Multi-frame, or both the CRC Multi-frame and Signaling Multi-frame, or the TS1 and TS16 over-
head.
In E1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate
the start of a frame.
RSFSn is updated/sampled on the active edge of the corresponding RSCKn. The active polarity of RSFSn is
selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
MRSFS: Multiplexed Receive Side System Frame Pulse for Link 1 ~ 4
In Receive Multiplexed mode, MRSFS inputs the pulse at a rate of integer multiple of 125 µs to indicate the
start of a frame on the multiplexed data bus. MRSFS is sampled on the active edge of MRSCK. The active
polarity of MRSFS is selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
RSFS[1:4]/MRSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
RSCK[1:4]: Receive Side System Clock for Link 1 ~ 4
In Receive Clock Master mode, the RSCKn pins output a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz
(for E1 mode) clock used to update the signal on the corresponding RSDn, RSIGn and RSFSn pins.
In Receive Clock Slave mode, the RSCKn pins input a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096
MHz clock used to update the signals on the corresponding RSDn and RSIGn pins and sample the signals on
the corresponding RSFSn pins. Selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSCK[1]
pin can be used for all four links.
MRSCK: Multiplexed Receive Side System Clock for Link 1 ~ 4
In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on
the corresponding MRSDA/MRSDB and MRSIGA/MRSIGB pins and sample the signal on the corresponding
MRSFS pin.
RSCK[1:4]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
TSD[1:4]: Transmit Side System Data for Link 1 ~ 4
The data stream from the system side is input on these pins.
In Transmit Clock Master mode, the TSDn pins are sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSDn pins
are sampled on the active edge of the corresponding TSCKn or all four TSDn pins are sampled on the active
edge of TSCK[1].
MTSDA[1] / MTSDB[1]: Multiplexed Transmit Side System Data A / B for Link 1 ~ 4
In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSDA[1] pin
or the MTSDB[1] pin is used to input the data stream. Using a byte-interleaved multiplexing scheme, the
MTSDA[1]/MTSDB[1] pins input the data for Link 1 to Link 4. The data on the MTSDA[1]/MTSDB[1] pins are
sampled on the active edge of MTSCK.
TSD[1:4]/MTSDA[1]/MTSDB[1] are Schmitt-triggered inputs.
15
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
February 25, 2008