82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 336

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

E1 Timeslot Control Register (00H ~ 1FH)
SUBST[2:0]:
SINV, OINV, EINV:
G56K, GAP:
Programming Information
IDT82P2284
SUBST[2:0]
Bit Name
When the GSUBST[2:0] bits (b2~0, E1-0D0H,...) are ‘000’, these bits select the replacement on a per-timeslot basis.
These three bits select how to invert the bits in the corresponding timeslot.
These bits are valid in Receive Clock Master mode when the PCCE bit (b0, E1-0D1H,...) is ‘1’.
Default
Bit No.
Type
others
000
001
010
011
SINV
0
0
0
0
1
1
1
1
G56K
X
No operation.
The data of the corresponding timeslot is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of the corresponding timeslot is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding timeslot is replaced by the µ-Law digital milliwatt pattern.
Reserved.
0
1
SUBST2
R/W
7
0
OINV
0
0
1
1
0
0
1
1
GAP
0
0
1
EINV
0
1
0
1
0
1
0
1
SUBST1
R/W
6
0
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding timeslot (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding timeslot (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding timeslot (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding timeslot.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding timeslot.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding timeslot (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding timeslot (bit 1 is the MSB).
The corresponding timeslot is not gapped.
Bit 8 (LSB) of the corresponding timeslot is gapped (no clock signal during the Bit 8).
The corresponding timeslot is gapped (no clock signal during the timeslot).
SUBST0
R/W
5
0
SINV
R/W
Replacement Selection
4
0
336
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit Inversion
Gap Mode
OINV
R/W
3
0
EINV
R/W
2
0
G56K
R/W
1
0
February 25, 2008
GAP
R/W
0
0