82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 276

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

E1 FRMR Interrupt Indication 1 (053H, 153H, 253H, 353H)
ISMFPI:
ICSMFPI:
SMFERI:
When one or more bits do not match, a single CAS Signaling Multi-Frame alignment pattern error event is generated. During out of CAS Signaling
Multi-Frame synchronization state, the CAS Signaling Multi-Frame Alignment Pattern Error detection is suspended.
ICMFPI:
CMFERI:
or more bits do not match, a single CRC Multi-Frame alignment pattern error event is generated. During out of CRC Multi-Frame synchronization
state, the CRC Multi-Frame Alignment Pattern Error detection is suspended.
CRCEI:
received CRC-4 of the next received CRC Sub Multi-Frame, a single CRC-4 error event is generated. During out of CRC Multi-Frame synchronization
state, the CRC-4 Error detection is suspended.
Programming Information
IDT82P2284
Bit Name
= 0: The received bit is not the first bit of each CAS Signaling Multi-Frame.
= 1: The first bit of each CAS Signaling Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CAS Signaling Multi-Frame synchronization state
= 0: The received bit is not the first bit of each CRC Sub Multi-Frame.
= 1: The first bit of each CRC Sub Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CRC Multi-Frame synchronization state.
When Signaling Multi-Frame is synchronized, the received Signaling Multi-Frame alignment signals are compared with the expected one (‘0000’).
= 0: No CAS Signaling Multi-Frame Alignment Pattern Error event is detected.
= 1: The CAS Signaling Multi-Frame Alignment Pattern Error event is detected.
This bit will be cleared if a ’1’ is written to it.
= 0: The received bit is not the first bit of each CRC Multi-Frame.
= 1: The first bit of each CRC Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CRC Multi-Frame synchronization state.
When CRC Multi-Frame is synchronized, the received CRC Multi-Frame alignment signals are compared with the expected one (‘001011’). If one
= 0: No CRC Multi-Frame Alignment Pattern Error event is detected.
= 1: The CRC Multi-Frame Alignment Pattern Error event is detected.
This bit will be cleared if a ’1’ is written to it.
When CRC Multi-Frame is synchronized and the local calculated CRC-4 of the current received CRC Sub Multi-Frame does not match the
= 0: No CRC-4 Error event is detected.
= 1: The CRC-4 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
Default
Bit No.
Type
ISMFPI
R
7
0
ICSMFPI
R
6
0
SMFERI
R
5
0
ICMFPI
R
4
0
276
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
CMFERI
R
3
0
CRCEI
R
2
0
FERI
R
1
0
February 25, 2008
COFAI
R
0
0