82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 174

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

T1/J1 FRMR Mode 1 (04EH, 14EH, 24EH, 34EH)
DDSC:
MIMICC:
M2O[2:1]:
synchronization.
Exceeding the threshold will lead to out of synchronization.
consists of the 6-bit DDS pattern and its following F-bit. Exceeding the threshold will lead to out of synchronization.
sliding Fs bits in Frame (2n) (0<n<12 and n=36) window. Exceeding the threshold will lead to out of synchronization.
Programming Information
IDT82P2284
Bit Name
This bit selects the synchronization criteria of T1 DM format.
= 0: If a correct DDS pattern is received before the first F-bit of a single correct Frame Alignment Pattern and there is no mimic pattern, the T1 DM
synchronization is acquired.
= 1: If a single correct Frame Alignment Pattern is received, and twelve correct DDS patterns before each F-bit of the correct Frame Alignment
Pattern are all detected, and there is no mimic pattern, the T1 DM synchronization is acquired.
This bit selects the synchronization criteria in SF format and ESF format.
In SF format:
= 0: When two consecutive Frame Alignment Patterns are received error free in the data stream, the SF is synchronized. In this case, the existence
of mimic patterns is ignored.
= 1: When two consecutive Frame Alignment Patterns are received error free in the data stream without mimic pattern, the SF is synchronized.
In ESF format:
= 0: When a single correct Frame Alignment Pattern and a single correct CRC-6 are found in the same frame, the ESF is synchronized. In this
case, the existence of mimic patterns is ignored.
= 1: When four consecutive Frame Alignment Patterns are detected error free in the received data stream without mimic pattern, the ESF is
synchronized.
In SF format, these two bits define the threshold of the F Bit Error numbers in N-bit sliding F bits window. Exceeding the threshold will lead to out of
In ESF format, these two bits define the threshold of the Frame Alignment Bit Error numbers in N-bit sliding Frame Alignment bits window.
In T1 DM format, these two bits define the threshold of the 7-bit pattern error numbers in N-pattern sliding 7-bit patterns window. The 7-bit pattern
In SLC-96 format, these two bits define the threshold of the Ft bit error numbers in N-bit sliding Ft bits window or the Fs bit error numbers in N-bit
Default
Bit No.
Type
7
M2O[1:0]
6
0 0
0 1
1 0
1 1
Reserved
5
Error Numbers
4
2
2
2
174
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DDSC
Reserved
R/W
3
0
N-Bit/Pattern Sliding Window
MIMICC
R/W
2
0
4
5
6
M2O1
R/W
1
0
February 25, 2008
M2O0
R/W
0
0