82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 326

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

E1 RPLC Configuration (0D0H, 1D0H, 2D0H, 3D0H)
SIGSNAP:
GSTRKEN:
GSUBST[2:0]:
E1 RPLC Control Enable (0D1H, 1D1H, 2D1H, 3D1H)
PCCE:
Programming Information
IDT82P2284
GSUBST[2:0]
Bit Name
Bit Name
This bit is valid when Signaling Multi-frame is in synchronization.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first Basic frame are locked and output on the RSIGn/MRSIGA(MRSIGB) pin
as the signaling bits of the current whole Signaling Multi-frame.
= 0: The replacement is performed on a per-timeslot basis by setting the STRKEN bit (b4, E1-ID-41~4FH & 51~5FH) in the corresponding timeslot.
= 1: The signaling bits (ABCD) of all timeslots are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, E1-ID-41~4FH &
51~5FH).
These bits select the replacement of all the timeslots.
= 0: Disable all the functions in the Receive Payload Control.
= 1: Enable all the functions in the Receive Payload Control.
Default
Default
Bit No.
Bit No.
Type
Type
others
000
001
010
011
The replacement is performed on a per-timeslot basis by setting the SUBST[2:0] bits (b7~5, E1-ID-00~1FH) in the corresponding timeslot.
The data of all timeslots is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of all timeslots is replaced by the A-Law digital milliwatt pattern.
The data of all timeslots is replaced by the µ-Law digital milliwatt pattern.
Reserved.
SIGSNAP
R/W
7
0
7
GSTRKEN
R/W
6
0
6
5
5
Reserved
Reserved
4
Replacement Selection
4
326
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
3
GSUBST2
R/W
2
0
2
GSUBST1
R/W
1
0
1
February 25, 2008
GSUBST0
PCCE
R/W
R/W
0
0
0
0