82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 9
82P2284BB
Manufacturer Part Number
82P2284BB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2284BB.pdf
(363 pages)
Specifications of 82P2284BB
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
82P2284BBG
Manufacturer:
NS/TI
Quantity:
5 705
- Current page: 9 of 363
- Download datasheet (3Mb)
List of Figures
Figure 1. 208-Pin PBGA (Top View) ........................................................................................................................................................................... 13
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 24
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 25
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 25
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 26
Figure 6. Transmit Path Monitoring (COAX) ............................................................................................................................................................... 26
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 27
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 30
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 30
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 30
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 43
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 44
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 46
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 61
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 62
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 66
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 66
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 72
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 73
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 73
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 74
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 75
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 75
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 76
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 81
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 82
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 82
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 83
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 84
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 84
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 85
Figure 32. DSX-1 Waveform Template ...................................................................................................................................................................... 101
Figure 33. T1/J1 Pulse Template Measurement Circuit ............................................................................................................................................ 101
Figure 34. E1 Waveform Template ............................................................................................................................................................................ 102
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................. 102
Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 113
Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 116
Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 116
Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 117
Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 117
Figure 41. JTAG Architecture .................................................................................................................................................................................... 340
Figure 42. JTAG State Diagram ................................................................................................................................................................................ 346
Figure 43. I/O Timing in Mode ................................................................................................................................................................................... 349
Figure 44. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 353
Figure 45. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 354
Figure 46. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 356
Figure 47. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 357
Figure 48. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 358
List of Figures
9
February 25, 2008
Related parts for 82P2284BB
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
TRANSLATION DEVICE DPI 80-PQFP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IDT PART
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC FREQ TIMING GENERATOR 28TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CLK DVR PLL 1:10 40VFQFPN
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CLK FANOUT BUFFER 1:18 32LQFP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CLK FANOUT BUFFER 1:18 32LQFP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CK505 VREG/RES 56TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC SDRAM CLK DVR 1:10 48-TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CLK DVR PLL 1:10 48TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC FLEXPC CLK PROGR P4 56-TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC FLEXPC CLK PROGR P4 56-TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC FLEXPC CLK PROGR P4 56-SSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC PLL CLK DRIVER 2.5V 28-TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet:
Part Number:
Description:
IC CLOCK DRIVER 2.5V 24-TSSOP
Manufacturer:
IDT, Integrated Device Technology Inc
Datasheet: