82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 95

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.20.2 HDLC TRANSMITTER
form HDLC packet data stream.
3.20.2.1 HDLC Channel Configuration
#2 & #3) per link are provided for HDLC insertion to the data stream to
be transmitted. In T1/J1 mode SF & SLC-96 formats, two HDLC Trans-
mitters (#2 & #3) per link are provided for HDLC insertion. In E1 mode,
three HDLC Transmitters (#1, #2 & #3) per link are provided for HDLC
insertion. Except in T1/J1 mode ESF & T1 DM formats, the HDLC
channel of HDLC Transmitter #1 is fixed in the DL bit (in ESF format)
and D bit in CH24 (in T1 DM format) respectively (refer to Table 13 &
Table 14), the other HDLC channel is configured as the follows:
the corresponding TDLEN bit is set to ‘1’.
Table 51: Related Bit / Register In Chapter 3.20.2.1
Functional Description
IDT82P2284
BITEN[7:0]
TDLEN3
TDLEN2
TDLEN1
The HDLC Transmitter inserts the data into the selected position to
In T1/J1 mode ESF & T1 DM formats, three HDLC Transmitters (#1,
• Set the EVEN bit and/or the ODD bit to select the even and/or odd
• Set the TS[4:0] bits to define the channel/timeslot of the assigned
• Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Transmitter will be enabled only if
TS[4:0]
EVEN
ODD
Bit
frames;
frame;
timeslot.
only) / THDLC2 Bit Select /
THDLC1 Assignment (E1
only) / THDLC2 Assign-
ment / THDLC3 Assign-
THDLC1 Bit Select (E1
THDLC Enable Control
THDLC3 Bit Select
Register
ment
089, 189, 289, 389 / 08A, 18A,
086, 186, 286, 386 / 087, 187,
088, 188, 288, 388 (E1 only) /
085, 185, 285, 385(E1 only) /
084, 184, 284, 384
Address (Hex)
28A, 38A
287, 387
95
3.20.2.2 HDLC Mode
selects the HDLC mode (per Q.921).
HDLC Mode
bits. The FIFO depth is 128 bytes. When it is full, it will be indicated by
the FUL bit. When it is empty, it will be indicated by the EMP bit.
bit, or if the data in the FIFO exceeds the upper threshold set by the
HL[1:0] bits, the data in the FIFO will be transmitted. The opening flag
(‘01111110’) will be prepended before the data automatically. The trans-
mission will not stop until the entire HDLC data are transmitted. Then the
2-byte FCS and the closing flag (‘01111110’) will be added to the end of
the HDLC data automatically. During the HDLC data transmission, a
zero is stuffed automatically into the serial output data if there are five
consecutive ’One’s ahead.
anytime when the ABORT bit is set. Or when the FIFO is empty and the
transmitted last byte is not the end of the current HDLC packet, the abort
sequence will be transmitted automatically.
to be transmitted, the 7E (Hex) flag will always be transmitted.
3.20.2.3 Interrupt Summary
threshold set by the LL[1:0] bits, it will be indicated by the RDY bit. When
there is a transition (from ‘0’ to ‘1’) on the RDY bit, the RDYI bit will be
set. In this case, if enabled by the RDYE bit, an interrupt will be reported
by the INT pin.
byte is not the end of the current HDLC packet, the UDRUNI bit will be
set. In this case, if enabled by the UDRUNE bit, an interrupt will be
reported by the INT pin.
3.20.2.4 Reset
to ‘1’ on the TRST bit. The reset will clear the FIFO.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Setting the THDLCM bit to ‘0’ (default) in the HDLC Transmitter
A FIFO buffer is used to store the HDLC data written in the DAT[7:0]
If an entire HDLC packet is stored in the FIFO indicated by the EOM
The abort sequence (‘01111111’) will be inserted to the HDLC packet
If the TDLEN bit is enabled and there is no HDLC packet in the FIFO
In the HDLC mode, when the data in the FIFO is below the lower
In the HDLC mode, when the FIFO is empty and the last transmitted
The HDLC Transmitter will be reset when there is a transition from ‘0’
February 25, 2008