82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 80

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.18 TRANSMIT SYSTEM INTERFACE
the device. The data input to the four links can be aligned with each
other or input independently. The timing clocks and framing pulses can
be provided by the system backplane or obtained from the processed
data of each link. The Transmit System Interface supports various
configurations to meet various requirements in different applications.
3.18.1 T1/J1 MODE
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each link at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the data is byte-interleaved from one high speed data stream and
inputs on the MTSDA1 (MTSDB1) pins at the bit rate of 8.192 Mb/s. The
demultiplexed data input to the four links is 2.048 Mb/s on the system
side and converted into 1.544 Mb/s format to the device.
Table 42: Operating Modes Selection In T1/J1 Transmit Path
Functional Description
IDT82P2284
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
3. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
TMU
X
The Transmit System Interface determines how to input the data to
In T1/J1 mode, the Transmit System Interface can be set in Non-
0
1
TMOD
E
X
0
1
G56K, GAP
/ FBITGAP
not all 0s
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
80
TSFSn; however in Transmit Clock Slave mode, TSCKn & TSFSn are
input to the device from outside.
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCKn, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
1.544 Mb/s (i.e., the line data rate), 2.048 Mb/s or 8.192 Mb/s. If the
backplane data rate is 2.048 Mb/s or 8.192 Mb/s, the Transmit System
Interface is in T1/J1 mode E1 rate and the data to be transmitted is
mapped to 1.544 Mb/s in device per 3 kinds of schemes.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In Transmit Clock Master mode, the device outputs TSCKn and
In the Transmit Clock Master mode, if TSCKn outputs pulses during
In the Transmit Clock Slave mode, the backplane data rate may be
Table 42 summarizes how to set the transmit system interface of
MTSCK, MTSFS, MTSDA[1],
MTSIGA[1] (MTSDB[1],
TSDn, TSIGn, TSCKn,
Transmit System Interface Pin
TSDn, TSIGn
MTSIGB[1])
TSFSn
Input
3
February 25, 2008
TSCKn,
Output
TSFSn
X
X