PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 112

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
REGISTER 8-3:
8.4
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
DS39940D-page 112
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5-0
Note 1:
Note:
U-0
U-0
—
—
Clock Switching Operation
Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
The Primary Oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation
011110 =



000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =



100001 =
100000 = Minimum frequency deviation
U-0
U-0
—
—
OSCTUN: FRC OSCILLATOR TUNE REGISTER
W = Writable bit
‘1’ = Bit is set
TUN5
R/W-0
U-0
—
(1)
TUN4
R/W-0
U-0
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
R/W-0
8.4.1
To enable clock switching, the FCKSM Configuration
bits in CW2 must be programmed to ‘00’. (Refer to
Section 26.1 “Configuration Bits” for further details.)
If the FCKSM Configuration bits are unprogrammed
(‘1x’), the clock switching function and Fail-Safe Clock
Monitor function are disabled; this is the default setting.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is dis-
abled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
U-0
—
(1)
ENABLING CLOCK SWITCHING
TUN2
R/W-0
U-0
—
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
TUN1
R/W-0
U-0
—
(1)
TUN0
R/W-0
U-0
—
(1)
bit 8
bit 0