PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 114

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

generate the two clock signals.
PIC24FJ64GB004 FAMILY
8.5
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled. Since this is well beyond the
maximum CPU clock speed, a method is provided to
internally generate both the USB and system clocks
from a single oscillator source. PIC24FJ64GB004 family
devices use the same clock structure as other PIC24FJ
devices, but include a two-branch PLL system to
The USB PLL block is shown in Figure 8-2. In this
system, the input from the primary oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed, divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed,
divide-by-3 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIV bits select the system clock
speed; available clock options are listed in Table 8-2.
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must man-
ually configure the PLL divider to generate the required
4 MHz output using the PLLDIV<2:0> Configuration
bits. This limits the choices for primary oscillator
frequency to a total of 8 possibilities, shown in
Table 8-3.
FIGURE 8-2:
8.5.1
When
PIC24FJ64GB004 family devices, users must always
observe these rules in configuring the system clock:
• For USB operation, the selected clock source
DS39940D-page 114
(EC, HS or XT) must meet the USB clock
tolerance requirements.
(4 MHz or
8 MHz)
Input from
POSC
Input from
FRC
using
Oscillator Modes and USB
Operation
FNOSC<2:0>
CONSIDERATIONS FOR USB
OPERATION
the
USB
USB PLL BLOCK
On-The-Go
 12
 8
 6
 5
 4
 3
 2
 1
PLLDIV<2:0>
111
110
101
100
011
010
001
000
module
4 MHz
in
96 MHz
PLL
TABLE 8-2:
TABLE 8-3:
• The Primary Oscillator/PLL modes are the only
• All oscillator modes are available; however, USB
Input Oscillator
oscillator configurations that permit USB opera-
tion. There is no provision to provide a separate
external clock source to the USB module.
operation is not possible when these modes are
selected. They may still be useful in cases where
other power levels of operation are desirable and
the USB module is not needed (e.g., the application
is Sleeping and waiting for bus attachment).
Frequency
 2
 3
MCU Clock Division
48 MHz
32 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
4 MHz
(CPDIV<1:0>)
None (00)
32 MHz
2 (01)
4 (10)
8 (11)
SYSTEM CLOCK OPTIONS
DURING USB OPERATION
VALID PRIMARY OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
XTPLL, ECPLL
XTPLL, ECPLL
Clock Mode
ECPLL
ECPLL
 2010 Microchip Technology Inc.
 8
 4
 2
 1
CPDIV<1:0>
11
10
01
00
Clock Frequency
Microcontroller
PLL Output
for System Clock
48 MHz Clock
for USB Module
32 MHz
16 MHz
8 MHz
4 MHz
(PLLDIV<2:0>)
PLL Division
12 (111)
8 (110)
6 (101)
5 (100)
4 (011)
3 (010)
2 (001)
1 (000)