PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 115

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.6
8.6.1
PIC24FJ64GB004 family devices do not have to set the
SOSCEN bit to use the secondary oscillator. Any module
requiring the SOSC (such as RTCC, Timer1 or DSWDT)
will automatically turn on the SOSC when the clock signal
is needed. The SOSC, however, has a long start-up time.
To avoid delays for peripheral start-up, the SOSC can be
manually started using the SOSCEN bit.
To use the secondary oscillator, the SOSCSEL<1:0>
bits (CW3<9:8>) must be configured in an oscillator
mode – either ‘11’ or ‘01’. Setting SOSCSEL to ‘00’
configures the SOSC pins for Digital mode, enabling
digital I/O functionality on the pins. Digital functionality
will not be available if the SOSC is configured in either
of the oscillator modes.
8.6.2
The secondary oscillator can operate in two distinct
levels of power consumption based on device configu-
ration. In Low-Power mode, the oscillator operates in a
low drive strength, low-power state. By default, the
oscillator uses a higher drive strength, and therefore,
requires more power. The Secondary Oscillator Mode
Configuration
determine the oscillator’s power mode. Programming
the SOSCSEL bits to ‘01’ selects low-power operation.
The lower drive strength of this mode makes the SOSC
more sensitive to noise and requires a longer start-up
time. When Low-Power mode is used, care must be
taken in the design and layout of the SOSC circuit to
ensure that the oscillator starts up and oscillates
properly.
8.6.3
The SOSC can also be configured to run from an
external 32 kHz clock source, rather than the internal
oscillator. In this mode, also referred to as Digital mode,
the clock source provided on the SCLKI pin is used to
clock any modules that are configured to use the
secondary oscillator. In this mode, the crystal driving
circuit is disabled and the SOSCEN bit (OSCCON<1>)
has no effect.
8.6.4
The pinout limitations on low pin count devices, such as
those in the PIC24FJ64GB004 family, may make the
SOSC more susceptible to noise than other PIC24F
devices. Unless proper care is taken in the design and
layout of the SOSC circuit, this external noise may
introduce inaccuracies into the oscillator’s period.
 2010 Microchip Technology Inc.
Secondary Oscillator (SOSC)
LOW-POWER SOSC OPERATION
BASIC SOSC OPERATION
EXTERNAL (DIGITAL) CLOCK
MODE (SCLKI)
SOSC LAYOUT CONSIDERATIONS
bits,
SOSCSEL<1:0>
(CW3<9:8>),
PIC24FJ64GB004 FAMILY
In general, the crystal circuit connections should be as
short as possible. It is also good practice to surround
the crystal circuit with a ground loop or ground plane.
For more information on crystal circuit design, please
refer to Section 6 “Oscillator” (DS39700) of the
“PIC24F Family Reference Manual”. Additional infor-
mation is also available in these Microchip Application
Notes:
• AN826, “Crystal Oscillator Basics and Crystal
• AN849, “Basic PICmicro
8.7
In addition to the CLKO output (F
tain oscillator modes, the device clock in the
PIC24FJ64GB004 family devices can also be configured
to provide a reference clock output signal to a port pin.
This feature is available in all oscillator configurations
and allows the user to select a greater range of clock
submultiples to drive external devices in the application.
This reference clock output is controlled by the
REFOCON register (Register 8-4). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the POSCEN bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
Selection for rfPIC
(DS00826)
(DS00849).
Reference Clock Output
®
and PICmicro
®
Oscillator Design”
OSC
DS39940D-page 115
/2) available in cer-
®
Devices”