PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 288

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

regulator Reset circuitry will generate a Brown-out
PIC24FJ64GB004 FAMILY
When waking up from Sleep mode with the regulator
disabled, T
To decrease the device wake-up time when operating
with the regulator disabled, the PMSLP bit can be set.
26.2.3
When
PIC24FJ64GB004 family devices also have a simple
brown-out capability. If the voltage supplied to the regu-
lator is inadequate to maintain the tracking level, the
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage specifications are
provided in Section 29.0 “Electrical Characteristics”.
26.2.4
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
never exceed V
26.2.5
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator automatically
places itself into Standby mode whenever the device
goes into Sleep mode by removing power from the
Flash program memory. This feature is controlled by
the PMSLP bit (RCON<8>). By default, this bit is
cleared, which enables Standby mode.
For PIC24FJ64GB004 family devices, the time
required for regulator wake-up from Standby mode is
controlled by the WUTSEL<1:0> Configuration bits
(CW3<11:10>). The default wake-up time for all
devices is 190 s, which is a Legacy mode provided to
match older PIC24F device wake-up times.
Implementing the WUTSEL Configuration bits provides
a fast wake-up option. When WUTSEL<1:0> = 01, the
regulator wake-up time is T
When the regulator’s Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered in
Sleep mode. That enables device wake-up without
waiting for T
consumption,
approximately 40 A higher than what it would be if the
regulator was allowed to enter Standby mode.
DS39940D-page 288
Note:
the
PM
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
For more information, see Section 29.0
“Electrical Characteristics”.
VOLTAGE REGULATOR STANDBY
MODE
PM
is used to determine the wake-up time.
. With PMSLP set, however, the power
DD
while
on-chip
by 0.3 volts.
in
PM
regulator
Sleep
, 10 s.
mode,
DDCORE
is
enabled,
will
DD
must
/I
PD
be
,
26.3
For PIC24FJ64GB004 family devices, the WDT is
driven by the LPRC Oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0>
Configuration bits (CW1<3:0>), which allow the selec-
tion of a total of 16 settings, from 1:1 to 1:32,768. Using
the prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
Watchdog Timer (WDT)
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
 2010 Microchip Technology Inc.
WDT
) of 1 ms in 5-bit mode, or