PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 122

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
9.2.4.10
V
ing from Deep Sleep functionally looks like a POR, the
technique described in Section 9.2.4.9 “Checking
and Clearing the Status of Deep Sleep Mode”
should be used to distinguish between Deep Sleep and
a true POR event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers, RTCC,
DSWDT, etc.) is reset.
DS39940D-page 122
DD
voltage is monitored to produce PORs. Since exit-
Power-on Resets (
PORs
)
9.2.4.11
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The DSEN bit is automatically cleared.
11. Read and clear the DPSLP status bit in RCON,
12. Read the DSGPRx registers (optional).
13. Once all state related configurations are
14. Application resumes normal operation.
Device exits Reset and begins to execute its
application code.
If DSWDT functionality is required, program the
appropriate Configuration bit.
Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
Enable and configure the RTCC (optional).
Write context data to the DSGPRx registers
(optional).
Enable the INT0 interrupt (optional).
Set the DSEN bit in the DSCON register.
Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
Device exits Deep Sleep when a wake-up event
occurs.
and the DSWAKE status bits.
complete, clear the RELEASE bit.
Summary of Deep Sleep Sequence
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