PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 255

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
21.1.3
The LENDIAN bit (CRCCON1<3>) is used to control
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction of the data that is shifted into the engine. The
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result.
21.1.4
The module generates an interrupt that is configurable
by the user for either of two conditions.
If CRCISEL is ‘0’, an interrupt is generated when the
VWORD<4:0> bits make a transition from a value of ‘1’
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated
after the CRC operation finishes and the module sets
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’
will not generate an interrupt.
21.1.5
To use the module for a typical CRC calculation:
1.
2.
3.
4.
5.
6.
7.
8.
 2010 Microchip Technology Inc.
Set the CRCEN bit to enable the module.
Configure the module for the desired operation:
a)
b)
c)
Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
set or no data is left
Clear old results by writing 00h to CRCWDATL
and CRCWDATH. CRCWDAT can also be left
unchanged to resume a previously halted
calculation.
Set the CRCGO bit to start calculation.
Write remaining data into the FIFO as space
becomes available.
When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
Read CRCWDATL and CRCWDATH for the
result of the calculation.
Program the desired polynomial using the
CRCXORL and CRCXORH registers, and
the PLEN<4:0> bits
Configure the data width and shift direction
using the DWIDTH and LENDIAN bits
Select the desired interrupt mode using the
CRCISEL bit
TYPICAL OPERATION
DATA SHIFT DIRECTION
INTERRUPT OPERATION
PIC24FJ64GB004 FAMILY
21.2
There are eight registers associated with the module:
• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH
The
(Register 21-1 and Register 21-2) control the operation
of the module and configure the various settings. The
CRCXOR registers (Register 21-3 and Register 21-4)
select the polynomial terms to be used in the CRC
equation. The CRCDAT and CRCWDAT registers are
each register pairs that serve as buffers for the
double-word, input data and CRC processed output,
respectively.
CRCCON1
Registers
and
CRCCON2
DS39940D-page 255
registers

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