MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1031
MC9S12XDP512CAL
Manufacturer Part Number
MC9S12XDP512CAL
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512CAL.pdf
(1348 pages)
Specifications of MC9S12XDP512CAL
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
91
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(16-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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24.0.7.9
This port is associated with the SPI1, . Port H pins PH[7:0] can be used for either general purpose
I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1. Refer to
Section 24.0.5.33, “Module Routing Register
Port H offers 8 I/O pins with edge triggered interrupt capability
24.0.7.10 Port J
This port is associated with CAN4, CAN0, IIC0. Port J pins PJ[7:4] and PJ[2:0] can be used for
either general purpose I/O, or with the CAN, IIC, or SCI subsystems. If IIC takes precedence the
associated pins become IIC open-drain output pins. The CAN4 pins can be re-routed. Refer to
Section 24.0.5.33, “Module Routing Register
Port J pins can be used with the routed CAN0 modules. Refer to
Routing Register
Port J offers 7 I/O pins with edge triggered interrupt capability
24.0.7.11 Port AD1
This port is associated with the ATD1. Port AD1 pins PAD15–PAD0 can be used for either general
purpose I/O, or with the ATD1 subsystem.
24.0.8
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to
rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port
interrupt enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when
it is in STOP or WAIT mode.
A digital filter on each pin prevents pulses
generating an interrupt. The minimum time varies over process conditions, temperature and
voltage
(Figure 24-69
Pin Interrupts
Port H
Port H is not available in 80-pin packages.
PJ[5,4,2,1,0] are not available in 80-pin packages.
PAD[15:8] are not available in 80-pin packages.
(MODRR)”.
and
Table
24-62).
(Figure
NOTE
NOTE
NOTE
(MODRR)”.
(MODRR)”.
24-70) shorter than a specified time from
(Section 24.0.8, “Pin
(Section 24.0.8, “Pin
Section 24.0.5.33, “Module
Interrupts”).
Interrupts”).
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