MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 413

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

9.5
The reset state of each individual bit is listed in
details the registers and their bit-fields.
9.6
IICV2 uses only one interrupt vector.
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
9.7
9.7.1
9.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
Freescale Semiconductor
1. Arbitration lost condition (IBAL bit set)
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
2. Update the IIC bus address register (IBAD) to define its slave address.
3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
frequency from system clock.
mode and interrupt enable or not.
Interrupt
Interrupt
Resets
Interrupts
Initialization/Application Information
IIC
IIC Programming Examples
Initialization Sequence
Offset
—
Vector
—
MC9S12XDP512 Data Sheet, Rev. 2.21
Priority
Table 9-8. Interrupt Summary
—
IBAL, TCF, IAAS
Section 9.3, “Memory Map and Register
bits in IBSR
Source
register
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
lost, transfer complete or address detect
conditions
Description
Definition,” which
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