MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 473

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

10.4.7.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
10.4.7.3
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
10.4.7.4
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode.
WUPE (see
10.4.7.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
conditions:
10.4.7.6
Interrupts are directly associated with one or more status flags in either the
Receiver Flag Register
Freescale Semiconductor
•
•
Overrun — An overrun condition of the receiver FIFO as described in
Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range
(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change,
which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Section 10.3.2.5, “MSCAN Receiver Flag Register
Receiver Interrupt Enable Register
Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
Section 10.3.2.1, “MSCAN Control Register 0
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Transmit Interrupt
Receive Interrupt
Wake-Up Interrupt
Error Interrupt
Interrupt Acknowledge
The dedicated interrupt vector addresses are defined in the
Interrupts
(CANRFLG)” or the
Interrupt Source
chapter.
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 10-37. Interrupt Vectors
(CANRIER)”).
Section 10.3.2.7, “MSCAN Transmitter Flag Register
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
NOTE
CCR Mask
I bit
I bit
I bit
I bit
(CANRFLG)” and
(CANCTL0)”) must be enabled.
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
Local Enable
Resets and
indicates one of the following
Section 10.3.2.5, “MSCAN
Section 10.3.2.6, “MSCAN
Section 10.4.2.3, “Receive
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