MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 608

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 16 Interrupt (S12XINTV1)
16.4.2.1
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This
way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The
new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel
which is configured to be handled by the CPU. The copying takes place when the interrupt vector is
fetched. The previous IPL is automatically restored by executing the RTI instruction.
16.4.3
The XINT module processes all exception requests to be serviced by the XGATE module. The overall
priority level of those exceptions is discussed in the subsections below.
16.4.3.1
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the
associated configuration register is set to 1 (please refer to
Configuration Data Registers
becomes the DMA priority which will be used to determine the highest priority DMA request to be
serviced next by the XGATE module. Additionally, DMA interrupts may be raised by the XGATE module
by setting one or more of the XGATE channel interrupt flags (using the SIF instruction). This will result
in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID
number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST bits are set.
The shared interrupt priority for the DMA interrupt requests is taken from the XGATE interrupt priority
configuration register (please refer to
(INT_XGPRIO)”). If more than one DMA interrupt request channel becomes active at the same time, the
channel with the highest vector address wins the prioritization.
16.4.4
The XINT module contains priority decoders to determine the priority for all interrupt requests pending
for the respective target.
There are two priority decoders, one for each interrupt request target (CPU, XGATE module). The function
of both priority decoders is basically the same with one exception: the priority decoder for the XGATE
module does not take the current interrupt processing level into account because XGATE requests cannot
be nested.
Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt
request could override the original exception that caused the CPU to request the vector. In this case, the
CPU will receive the highest priority vector and the system will process this exception instead of the
original request.
608
XGATE Requests
Priority Decoders
Interrupt Priority Stack
XGATE Request Prioritization
(INT_CFDATA0–7)”). The priority level setting (PRIOLVL) for this channel
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 16.3.1.2, “XGATE Interrupt Priority Configuration Register
Section 16.3.1.4, “Interrupt Request
Freescale Semiconductor