MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 289

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
Logical Triadic
Arithmetic Triadic
Branches
Load and Store Instructions
Bit Field Instructions
Logic Immediate Instructions
AND RD, RS1, RS2
OR RD, RS1, RS2
XNOR RD, RS1, RS2
SUB RD, RS1, RS2
SBC RD, RS1, RS2
ADD RD, RS1, RS2
ADC RD, RS1, RS2
BCC REL9
BCS REL9
BNE REL9
BEQ REL9
BPL REL9
BMI REL9
BVC REL9
BVS REL9
BHI REL9
BLS REL9
BGE REL9
BLT REL9
BGT REL9
BLE REL9
BRA REL10
LDB RD, (RB, #OFFS5)
LDW RD, (RB, #OFFS5)
STB RS, (RB, #OFFS5)
STW RS, (RB, #OFFS5)
LDB RD, (RB, RI)
LDW RD, (RB, RI)
STB RS, (RB, RI)
STW RS, (RB, RI)
LDB RD, (RB, RI+)
LDW RD, (RB, RI+)
STB RS, (RB, RI+)
STW RS, (RB, RI+)
LDB RD, (RB, –RI)
LDW RD, (RB, –RI)
STB RS, (RB, –RI)
STW RS, (RB, –RI)
BFEXT RD, RS1, RS2
BFINS RD, RS1, RS2
BFINSI RD, RS1, RS2
BFINSX RD, RS1, RS2
ANDL RD, #IMM8
Functionality
Table 6-17. Instruction Set Summary (Sheet 2 of 3)
MC9S12XDP512 Data Sheet, Rev. 2.21
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
13
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
12
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
11
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
RD
RD
RD
RD
RD
RD
RD
RD
RD
RS
RS
RD
RD
RS
RS
RD
RD
RS
RS
RD
RD
RS
RS
RD
RD
RD
RD
RD
9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
For compare use SUB R0,Rs1,Rs2
8
7
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
6
Chapter 6 XGATE (S12XGATEV2)
REL10
5
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
4
IMM8
RS2
RS2
RS2
RS2
RS2
RS2
RS2
RS2
RS2
RS2
RS2
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
3
OFFS5
OFFS5
OFFS5
OFFS5
2
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
289
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1